scholarly journals Reconfigurable modular arithmetic logic unit supporting high-performance RSA and ECC over GF(p)

2007 ◽  
Vol 94 (5) ◽  
pp. 501-514 ◽  
Author(s):  
K. Sakiyama ◽  
N. Mentens ◽  
L. Batina ◽  
B. Preneel ◽  
I. Verbauwhede
Keyword(s):  
High Performance ◽  
Modular Arithmetic ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

VLSI Design ◽  
2002 ◽  
Vol 14 (3) ◽  
pp. 249-258 ◽  
Author(s):  
Kiseon Cho ◽  
Minkyu Song
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Experimental Results ◽  
Cmos Process ◽  
Leaf Cell ◽  
Arithmetic Logic Unit ◽  
Barrel Shifter ◽  
Layout Technique ◽  
Logic Unit

In general, an arithmetic logic unit (ALU) of a DSP core is composed of an adder, multiplier and shifter. In order to obtain a high-performance 32-bit ALU, in this paper, an adaptive leaf-cell based layout technique is proposed. Thus novel architectures of 64-bit adder, 32 × 32-bit multiplier, and 32-bit shifter are proposed. The architecture of the proposed 64-bit adder is based on the conditional select addition with regular adaptive multiplexers. Secondly, novel optimized data compressors with a compound logic are proposed in a 32 × 32-bit multiplier. Finally, a shift algorithm with a pre-mask decoder is proposed for the 32-bit barrel shifter. They have been fabricated with 0.25 μm 1-poly 5-metal CMOS process, and we have obtained desired experimental results.

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

2017 ◽  
Vol 9 (4) ◽  
pp. 04018-1-04018-4
Author(s):  
K. Nehru ◽  
◽  
T. Nagarjuna ◽  
G. Vijay ◽  
◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Arithmetic Logic Unit ◽  
Logic Unit

Improving Performance of a Multi-Bit Arithmetic Logic Unit

2021 ◽  
Vol 26 (1) ◽  
pp. 40-53
Author(s):  
A.N. Yakunin ◽  
◽  
Aung Myo San ◽  
Khant Win ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Operating Time ◽  
Arithmetic Logic Unit ◽  
Maximum Delay ◽  
Sequential Organization ◽  
Quartus Ii ◽  
Logic Unit

In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

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