FPGA implementation of the block-matching algorithm for motion estimation in image coding

1996 ◽  
pp. 146-155 ◽  
Author(s):  
César Sanz ◽  
Laura Zulueta ◽  
Juan M. Meneses
Keyword(s):  
Motion Estimation ◽  
Image Coding ◽  
Fpga Implementation ◽  
Block Matching ◽  
Matching Algorithm ◽  
Block Matching Algorithm

LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS

2000 ◽  
Vol 10 (05n06) ◽  
pp. 229-237
Author(s):  
KYUNG-SAENG KIM ◽  
KWYRO LEE
Keyword(s):  
Motion Estimation ◽  
Data Transfer ◽  
Power Saving ◽  
Block Matching ◽  
Embedded Memory ◽  
Data Transfer Rate ◽  
Matching Algorithm ◽  
Block Matching Algorithm ◽  
Data Reading ◽  
Full Search

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

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