Clock Skew Scheduling and Clock Tree Synthesis

2008 ◽  
pp. 71-96
Keyword(s):  
Clock Skew ◽  
Clock Tree ◽  
Clock Tree Synthesis ◽  
Clock Skew Scheduling ◽  
Tree Synthesis

scholarly journals Post-CTS Delay Insertion

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Jianchao Lu ◽  
Baris Taskin
Keyword(s):  
Programming Model ◽  
Optimization Method ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Period ◽  
Clock Networks ◽  
Average Improvement ◽  
Clock Tree Synthesis ◽  
Clock Skew Scheduling ◽  
Tree Synthesis

A post-clock-tree-synthesis (post-CTS) optimization method is proposed that suggests delay insertion at the leaves of the clock tree in order to implement a limited version of clock skew scheduling. Delay insertion is limited on each clock tree branch simultaneous with a global monitoring of the total amount of delay insertion. The delay insertion for nonzero clock skew operation is performed only at the clock sinks in order to preserve the structure and the optimizations implemented in the clock tree synthesis stage. The methodology is implemented as a linear programming model amenable to two design objectives: fixing timing violations or optimizing the clock period. Experimental results show that the clock networks of the largest ISCAS'89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159    clock period per clock path on average). It is also shown that the majority of the clock period improvement achievable through unrestricted clock skew scheduling are obtained through very limited insertion (43% average improvement through 10% of max insertion).

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650142 ◽  
Author(s):  
Kamineni Sumanth Kumar ◽  
John Reuben
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Three Dimensional ◽  
Buffer Insertion ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Tree Synthesis ◽  
3D Integrated Circuits ◽  
Tree Synthesis

Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of ‘More than Moore’ while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25–28% reduction in buffer count and 25–29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31–38% reduction in buffer count and 32–39% reduction in power.

scholarly journals Analysis of Clock trees for optimization through Multi point Clock Tree Synthesis

2020 ◽  
Vol 8 (5) ◽  
pp. 1879-1882
Keyword(s):  
Rapid Development ◽  
Synthesis Method ◽  
Deep Submicron ◽  
Vlsi Circuits ◽  
Clock Skew ◽  
Clock Tree ◽  
Timing Closure ◽  
Clock Tree Synthesis ◽  
Tree Synthesis ◽  
The Given

With rapid development of deep submicron (DSM) VLSI circuits design, building clock tree with minimal insertion delays and minimal skews has turned out to be challenging. In this Paper for a given specified block with a latency of 530 ns it is aimed to achieve a latency of 400ns and achieve optimal power. Here a Clock Tree Synthesis method is used to reduce the latency and obtain the timing closure for the given block. The analysis is made and compared in terms of clock skew and insertion delay by varying the tap points. In this process of achieving the timing closure it is observed power has optimized by selecting the appropriate tap points.

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

2011 ◽  
Vol E94-C (3) ◽  
pp. 288-295 ◽  
Author(s):  
Kazuyoshi TAKAGI ◽  
Yuki ITO ◽  
Shota TAKESHIMA ◽  
Masamitsu TANAKA ◽  
Naofumi TAKAGI
Keyword(s):  
Clock Tree ◽  
Clock Tree Synthesis ◽  
Tree Synthesis
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