Fault-Tolerant Reconfigurable On-Chip-Network

Energy-Efficient Fault-Tolerant Systems ◽

10.1007/978-1-4614-4193-9_6 ◽

2013 ◽

pp. 211-240

Author(s):

Mohammad Hosseinabady ◽

Jose L. Nunez-Yanez

Keyword(s):

Fault Tolerant ◽

On Chip

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Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

Journal of Systems Architecture ◽

10.1016/j.sysarc.2021.102026 ◽

2021 ◽

Vol 116 ◽

pp. 102026

Author(s):

P. Veda Bhanu ◽

Soumya J.

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Application Mapping ◽

On Chip

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RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection

2021 22nd International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed51717.2021.9424265 ◽

2021 ◽

Author(s):

Yu-Kai Chuang ◽

Yong Zhong ◽

Yi-Hao Cheng ◽

Bo-Yi Yu ◽

Shao-Yun Fang ◽

...

Keyword(s):

Optical Networks ◽

Fault Tolerant ◽

Networks On Chip ◽

On Chip

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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081674 ◽

2011 ◽

Author(s):

Zhiliang Qian ◽

Ying Fei Teh ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

Chip Design ◽

On Chip

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How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

2010 European Dependable Computing Conference ◽

10.1109/edcc.2010.35 ◽

2010 ◽

Cited By ~ 5

Author(s):

Matthias Függer ◽

Andreas Dielacher ◽

Ulrich Schmid

Keyword(s):

Fault Tolerant ◽

Clock Generation ◽

Systems On Chip ◽

Speed Up ◽

On Chip

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Reliability analysis of a fault-tolerant RISC-V system-on-chip

Microelectronics Reliability ◽

10.1016/j.microrel.2021.114346 ◽

2021 ◽

Vol 125 ◽

pp. 114346

Author(s):

Douglas Almeida Santos ◽

Lucas Matana Luza ◽

Luigi Dilillo ◽

Cesar Albenes Zeferino ◽

Douglas Rossi Melo

Keyword(s):

Reliability Analysis ◽

Fault Tolerant ◽

System On Chip ◽

On Chip

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Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2012.6322894 ◽

2012 ◽

Cited By ~ 2

Author(s):

Anup Das ◽

Akash Kumar ◽

Bharadwaj Veeravalli

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Network Interface ◽

On Chip ◽

Spatial Division Multiplexing

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A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip

2018 11th International Workshop on Network on Chip Architectures (NoCArc) ◽

10.1109/nocarc.2018.8541212 ◽

2018 ◽

Cited By ~ 1

Author(s):

Pieter Stroobant ◽

Sergi Abadal ◽

Wouter Tavernier ◽

Eduard Alarcon ◽

Didier Colle ◽

...

Keyword(s):

Routing Protocol ◽

Fault Tolerant ◽

Network On Chip ◽

On Chip

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Fault-tolerant routing methodology for Networks-on-Chip

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2017.8106993 ◽

2017 ◽

Author(s):

S. Savva

Keyword(s):

Fault Tolerant ◽

Networks On Chip ◽

On Chip

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Design of a Fault-Tolerant DRAM with New On-Chip ECC

Defect and Fault Tolerance in VLSI Systems ◽

10.1007/978-1-4615-6799-8_8 ◽

1989 ◽

pp. 85-92 ◽

Cited By ~ 4

Author(s):

P. Mazumder

Keyword(s):

Fault Tolerant ◽

On Chip

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Towards fault-tolerant digital microfluidic lab-on-chip: Defects, fault modeling, testing, and reconfiguration

2008 IEEE Biomedical Circuits and Systems Conference ◽

10.1109/biocas.2008.4696941 ◽

2008 ◽

Cited By ~ 19

Author(s):

Krishnendu Chakrabarty

Keyword(s):

Fault Tolerant ◽

Fault Modeling ◽

Lab On Chip ◽

On Chip ◽

Digital Microfluidic

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