Low Power Clock Distribution

Low Power Resonant Rotary Global Clock Distribution Network Design

10.17918/etd-4573 ◽

2021 ◽

Author(s):

Ying Teng

Keyword(s):

Low Power ◽

Network Design ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

Global Clock ◽

Clock Distribution Network

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Low-power clock distribution using multiple voltages and reduced swings

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2002.1043334 ◽

2002 ◽

Vol 10 (3) ◽

pp. 309-318 ◽

Cited By ~ 63

Author(s):

J. Pangjun ◽

S.S. Sapatnekar

Keyword(s):

Low Power ◽

Clock Distribution

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A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

2011 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2011.80 ◽

2011 ◽

Cited By ~ 4

Author(s):

Naveen Kumar Kancharapu ◽

Marshnil Dave ◽

Veerraju Masimukkula ◽

Maryam Shojaei Baghini ◽

Dinesh Kumar Sharma

Keyword(s):

Low Power ◽

Distribution Network ◽

Current Mode ◽

Cmos Technology ◽

Clock Distribution ◽

Clock Distribution Network

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Design of Low power & High Performance Multi Source H-Tree Clock Distribution Network

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) ◽

10.1109/vlsidcs47293.2020.9179954 ◽

2020 ◽

Author(s):

V.G. Srivatsa ◽

Arunkumar P. Chavan ◽

Divakar Mourya

Keyword(s):

Low Power ◽

High Performance ◽

Distribution Network ◽

Clock Distribution ◽

Clock Distribution Network

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Package clock distribution design optimization for high-speed and low-power VLSIs

IEEE Transactions on Components Packaging and Manufacturing Technology Part B ◽

10.1109/96.554527 ◽

1997 ◽

Vol 20 (1) ◽

pp. 56-63 ◽

Cited By ~ 12

Author(s):

Qing Zhu ◽

S. Tam

Keyword(s):

Low Power ◽

Design Optimization ◽

High Speed ◽

Clock Distribution

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Buffer insertion and sizing under process variations for low power clock distribution

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95 ◽

10.1145/217474.217576 ◽

1995 ◽

Cited By ~ 37

Author(s):

Joe G. Xi ◽

Wayne W. M. Dai

Keyword(s):

Low Power ◽

Process Variations ◽

Clock Distribution ◽

Buffer Insertion

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Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 ◽

10.1145/1283780.1283795 ◽

2007 ◽

Cited By ~ 2

Author(s):

Sherif A. Tawfik ◽

Volkan Kursun

Keyword(s):

Temperature Gradient ◽

Low Power ◽

Clock Distribution

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Slew and Skew Analysis for Low Power Clock Tree Synthesis Using Clock Distribution Networks

Sensor Letters ◽

10.1166/sl.2019.4123 ◽

2019 ◽

Vol 17 (8) ◽

pp. 641-653

Author(s):

R. Rajalakshmi ◽

S. M. Ramesh ◽

P. Sivakumar

Keyword(s):

Low Power ◽

Distribution Networks ◽

Clock Distribution ◽

Clock Tree ◽

Clock Distribution Networks ◽

Clock Tree Synthesis ◽

Tree Synthesis

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Low-power bufferless resonant clock distribution networks

2007 50th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2007.4488725 ◽

2007 ◽

Cited By ~ 3

Author(s):

Behzad Mesgarzadeh ◽

Martin Hansson ◽

Atila Alvandpour

Keyword(s):

Low Power ◽

Distribution Networks ◽

Clock Distribution ◽

Clock Distribution Networks ◽

Resonant Clock

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Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2000976 ◽

2008 ◽

Vol 16 (9) ◽

pp. 1251-1256 ◽

Cited By ~ 12

Author(s):

Lin Zhang ◽

A. Carpenter ◽

B. Ciftcioglu ◽

A. Garg ◽

M. Huang ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Clock Distribution ◽

Distribution Scheme

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