On Configuring a Testbed for Dependability Experiments: Guidelines and Fault Injection Case Study

2020 ◽  
pp. 419-433 ◽  
Author(s):  
João R. Campos ◽  
Ernesto Costa ◽  
Marco Vieira
Keyword(s):  
Fault Injection

Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study

2011 ◽  
Author(s):  
M. Portela-Garcia ◽  
A. Lindoso ◽  
L. Entrena ◽  
M. Garcia-Valderas ◽  
C. Lopez-Ongil ◽  
...  
Keyword(s):  
Fault Injection ◽  
Injection Technique ◽  
Software Robustness

Virtual Verification and Validation of Automotive System

2019 ◽  
Vol 28 (04) ◽  
pp. 1950071
Author(s):  
Mona Safar ◽  
Magdy A. El-Moursy ◽  
Mohamed Abdelsalam ◽  
Ayman Bakr ◽  
Keroles Khalil ◽  
...  
Keyword(s):  
Fault Injection ◽  
Electronic Control Unit ◽  
Control Unit ◽  
Verification And Validation ◽  
System Level ◽  
Development Cycle ◽  
Virtual Platform ◽  
On Chip ◽  
Automotive System

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

scholarly journals Model-based On-board Decision Making for Autonomous Aircraft

2019 ◽  
Vol 11 (1) ◽  
Author(s):  
Johann Martin Schumann ◽  
Nagabhushan Mahadevan ◽  
Michael Lowry ◽  
Gabor Karsai
Keyword(s):  
Health Management ◽  
Fault Injection ◽  
Search Algorithm ◽  
Failure Detection ◽  
Modeling Framework ◽  
Backtracking Search ◽  
Model Based ◽  
Automatic Planning ◽  
Board Decision Making

Powerful, small and lightweight sensors in combination with advanced failure detection, diagnosis, and prognostics techniques provide up-to-date data on the health status of a Unmanned Aerial System (UAS). In an autonomous UAS, this information must be used for automatic planning and execution of contingency actions to keep the UAS safe in adverse conditions.We present DM (Decision Maker), a software component which uses model-based reasoning, backtracking search to iteratively construct contingency plansthat are safe for the UAS to execute and pose minimal interruption to the mission goals. The DM, which has been developed within the NASA Autonomous Operating System (AOS) project thus fills the gap between Prognostics and Health Management and autonomous flight operations.In this paper, we describe DM and its reasoning/search algorithm and present the supporting modeling framework for the construction of system and fault models. An flight with a DJI S1000+ octocopter with fault injection will be used as our case study.

scholarly journals Robust Convolutional Neural Networks in SRAM-based FPGAs: a Case Study in Image Classification

2021 ◽  
Vol 16 (2) ◽  
pp. 1-12
Author(s):  
Fabio Benevenuti ◽  
Fernanda Lima Kastensmidt ◽  
Ádria Barros de Oliveira ◽  
Nemitala Added ◽  
Vitor Ângelo Paulino de Aguiar ◽  
...  
Keyword(s):  
Image Classification ◽  
Hardware Implementation ◽  
Fault Injection ◽  
Fine Tuning ◽  
Traffic Sign ◽  
Sign Recognition ◽  
User Data ◽  
Floating Point Number ◽  
Xilinx Fpga

This work discusses the main aspects of vulnerability and degradation of accuracy of an image classification engine implemented into SRAM-based FPGAs under faults. The image classification engine is an all-convolutional neural-network (CNN) trained with a dataset of traffic sign recognition benchmark. The Caffe and Ristretto frameworks were used for CNN training and fine-tuning while the ZynqNet inference engine was adopted as hardware implementation on a Xilinx 28 nm SRAM-based FPGA. The CNN under test was generated using an evolutive approach based on genetic algorithm. The methodologies for qualifying this CNN under faults is presented and both heavy-ions accelerated irradiation and emulated fault injection were performed. To cross validate results from radiation and fault injection, different implementations of the same CNN were tested using reduced arithmetic precision and protection of user data by Hamming codes, in combination with configuration memory healing by the scrubbing mechanism available in Xilinx FPGA. Some of these alternative implementations increased significantly the mission time of the CNN, when compared to the original ZynqNet operating on 32 bits floating point number, and the experiment suggests areas for further improvements on the fault injection methodology in use.

scholarly journals Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

2016 ◽  
Vol 11 (3) ◽  
pp. 185-191
Author(s):  
Carlos J. G. Aguilera ◽  
Cristiano P. Chenet ◽  
Tiago R. Balen
Keyword(s):  
Fault Tolerant ◽  
Fault Injection ◽  
Random Sequence ◽  
Masking Effect ◽  
Mixed Signal ◽  
Sram Memory ◽  
On Chip ◽  
Sequence Generator ◽  
Design Diversity

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

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