Virtual Verification and Validation of Automotive System

2019 ◽  
Vol 28 (04) ◽  
pp. 1950071
Author(s):  
Mona Safar ◽  
Magdy A. El-Moursy ◽  
Mohamed Abdelsalam ◽  
Ayman Bakr ◽  
Keroles Khalil ◽  
...  
Keyword(s):  
Fault Injection ◽  
Electronic Control Unit ◽  
Control Unit ◽  
Verification And Validation ◽  
System Level ◽  
Development Cycle ◽  
Virtual Platform ◽  
On Chip ◽  
Automotive System

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

scholarly journals ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1179
Author(s):  
Jonatan Sánchez ◽  
Antonio da Silva ◽  
Pablo Parra ◽  
Óscar R. Polo ◽  
Agustín Martínez Hellín ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Architectural Design ◽  
Fault Injection ◽  
Control Unit ◽  
Tolerance Mechanisms ◽  
Efficient Data ◽  
Instrument Control ◽  
Virtual Platform ◽  
Hardware Platforms ◽  
The University

Multicore hardware platforms are being incorporated into spacecraft on-board systems to achieve faster and more efficient data processing. However, such systems lead to increased complexity in software development and represent a considerable challenge, especially concerning the runtime verification of fault-tolerance requirements. To address the ever-challenging verification of this kind of requirement, we introduce a LEON4 multicore virtual platform called LeonViP-MC. LeonViP-MC is an evolution of a previous development called Leon2ViP, carried out by the Space Research Group of the University of Alcalá (SRG-UAH), which has been successfully used in the development and testing of the flight software of the instrument control unit (ICU) of the energetic particle detector (EPD) on board the Solar Orbiter. This paper describes the LeonViP-MC architectural design decisions oriented towards fault-injection campaigns to verify software fault-tolerance mechanisms. To validate the simulator, we developed an ARINC653 communications channel that incorporates fault-tolerance mechanisms and is currently being used to develop a hypervisor level for the GR740 platform.

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

2014 ◽  
pp. 150-179
Author(s):  
Haoyuan Ying ◽  
Klaus Hofmann ◽  
Thomas Hollstein
Keyword(s):  
Embedded Systems ◽  
Design Optimization ◽  
Optimization Methods ◽  
Design Methods ◽  
System Level ◽  
System Level Design ◽  
Level Design ◽  
On Chip ◽  
Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

scholarly journals Verification and validation of an automated robot inspection cell for automotive body-in-white: a use case for the VALU3S ECSEL project

2021 ◽  
Vol 1 ◽  
pp. 115
Author(s):  
Alper Kanak ◽  
Salih Ergun ◽  
Ahmet Yazıcı ◽  
Metin Ozkan ◽  
Gürol Çokünlü ◽  
...  
Keyword(s):  
Fault Injection ◽  
Verification And Validation ◽  
System Level ◽  
Automated Systems ◽  
Component Level ◽  
Horizon 2020 ◽  
Automotive Body ◽  
Recent Developments ◽  
Injection Techniques ◽  
Body In White

Verification and validation (V&V) of systems, and system of systems, in an industrial context has never been as important as today. The recent developments in automated cyber-physical systems, digital twin environments, and Industry 4.0 applications require effective and comprehensive V&V mechanisms. Verification and Validation of Automated Systems' Safety and Security (VALU3S), a Horizon 2020 Electronic Components and Systems for European Leadership Joint Undertaking (ECSEL-JU) project started in May 2020, aims to create and evaluate a multi-domain V&V framework that facilitates evaluation of automated systems from component level to system level, with the aim of reducing the time and effort needed to evaluate these systems. VALU3S focuses on V&V for the requirements of safety, cybersecurity, and privacy (SCP). This paper mainly focuses on the elaboration of one of the 13 use cases of VALU3S to identify the SCP issues in an automated robot inspection cell that is being actively used for the quality control assessment of automotive body-in-white. The joint study here embarks on a collaborative approach that puts the V&V methods and workflows for the robotic arms safety trajectory planning and execution, fault injection techniques, cyber-physical security vulnerability assessment, anomaly detection, and SCP countermeasures required for remote control and inspection. The paper also presents cross-links with ECSEL-JU goals and the current advancements in the market and scientific and technological state-of-play.

A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs

2013 ◽  
Vol 4 (1) ◽  
pp. 22-41 ◽  
Author(s):  
Antonio Miele ◽  
Christian Pilato ◽  
Donatella Sciuto
Keyword(s):  
System Level ◽  
System Level Design ◽  
Simulation Environment ◽  
Processing Application ◽  
Systems On Chip ◽  
Simulation Based ◽  
Level Design ◽  
On Chip ◽  
Timing Models

The efficient analysis and exploration of mapping solutions of a parallel application on a heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) is usually a challenging task in system-level design, in particular when the architecture integrates hardware cores that may expose reconfigurable features. This paper proposes a system-level design framework based on SystemC simulations for fulfilling this task, featuring (i) an automated flow for the generation of timing models for the hardware cores starting from the application source code, (ii) an enhanced simulation environment for SystemC architectures enabling the specification and modification of mapping choices only by changing an XML descriptor, and (iii) a flexible controller of the simulation environment supporting the exploration of various mapping solutions featuring a customizable engine. The proposed framework has been validated with a case study considering an image processing application to show the possibility to automatically exploring alternative solutions onto a reconfigurable MPSoC platform.

scholarly journals Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Zineb El Hariti ◽  
Abdelhakim Alali ◽  
Mohamed Sadik ◽  
Kaoutar Aamali
Keyword(s):  
High Performance ◽  
System Level ◽  
Limiting Factor ◽  
Power Budget ◽  
Technology Roadmap ◽  
Systems On Chip ◽  
Limited Power ◽  
Virtual Platform ◽  
On Chip ◽  
Technology Nodes

Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

scholarly journals Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

2016 ◽  
Vol 11 (3) ◽  
pp. 185-191
Author(s):  
Carlos J. G. Aguilera ◽  
Cristiano P. Chenet ◽  
Tiago R. Balen
Keyword(s):  
Fault Tolerant ◽  
Fault Injection ◽  
Random Sequence ◽  
Masking Effect ◽  
Mixed Signal ◽  
Sram Memory ◽  
On Chip ◽  
Sequence Generator ◽  
Design Diversity

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

scholarly journals ASFIT: AUTOSAR-Based Software Fault Injection Test for Vehicles

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 850
Author(s):  
Jihyun Park ◽  
Byoungju Choi
Keyword(s):  
Fault Injection ◽  
Electronic Control Unit ◽  
Empirical Studies ◽  
Control Unit ◽  
Superior Performance ◽  
Software Faults ◽  
Automotive Software ◽  
Iso 26262 ◽  
Design And Testing ◽  
Types Of Faults

With recent increases in the amount of software installed in vehicles, the probability of automotive software faults that lead to accidents has also increased. Because automotive software faults can lead to serious accidents or even mortalities, vehicle software design and testing must consider safety a top priority. ISO 26262 recommends fault injection testing as a measure to verify the functional safety of vehicles. However, the standard does not clearly specify when and where faults should be injected, and the tools to support fault injection testing for automotive software are also insufficient. In the present study, we define faults that may occur in Automotive Open System Architecture (AUTOSAR)-based automotive software and propose a fault injection method to be applied during the software development process. The proposed method can inject different types of faults that may occur in AUTOSAR-based automotive software, such as access, asymmetric, and timing errors, while minimizing performance degradation due to fault injection, and without using any separate hardware devices. The superior performance of the proposed method is demonstrated through empirical studies applied to fault injection testing of a range of vehicle electronic control unit software.

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