Time-to-Failure Models for Selected Failure Mechanisms in Integrated Circuits

Author(s):  
J. W. McPherson
2012 ◽  
Vol 548 ◽  
pp. 527-531 ◽  
Author(s):  
Xiao Yu Liu ◽  
Jiang Shao ◽  
Xing Hao Wang ◽  
Feng Ming Lu

Electrostatic discharge (ESD) is a single, fast, high current transfer of electrostatic charge between two objects at different electrostatic potentials, and it is one of the most important failure mechanisms in integrated circuits due to their complex operation condition. The modes, mechanism, and models of the ESD failure were discussed. Firstly failure modes of ESD were classified and the failure mechanisms were described. Then three failure models including Wunsch and Bell model, Speakman model and Tasca model were summarized. The differences of the assumption and application area of these models were discussed in detail later. At last, suggestions for future studying ESD physics of failure model were proposed.


Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.


2020 ◽  
Vol 2020 (1) ◽  
pp. 000100-000105
Author(s):  
P.E. Chris South

Abstract Acceleration factors (AF) are key to designing an effective accelerated life test (ALT). They represent the ratio of the time in field to the time in test for a particular event to occur (typically a failure event related to a specific failure mechanism). Time to failure for a device generally correlates with the amount of stress applied (the higher the stress, the quicker the device will fail), and failure models exist to mathematically define that correlation for various failure mechanisms. This allows for use of a higher stress in test than in the field, thereby providing an acceleration factor that shortens the time in test to demonstrate a failure-free time period. ALT can take the form of qualitative or quantitative testing. The latter is used to determine the life characteristics of the device with some reliability and confidence level. Usage rate acceleration and higher stress acceleration can be used. It is important to consider the design limits of the device based on its specification and material properties, and limit the stress levels in test so as not to induce failure mechanisms that the device would not otherwise have experienced in the field. ALT results are used to make life predictions for the device tested. With no failures, the test results demonstrate the required reliability and confidence level metrics for the failure mechanism of interest. With several failures, a reliability software tool can be used with the appropriate analysis method, rank method, and confidence bounds method chosen in order to extrapolate to an expected life in test. The equivalent field life is based on multiplying the expected life in test by the AF. If the field stress and/or test stress are not constant, there are multiple acceleration factors to utilize. As a result, an equivalent acceleration factor needs to be calculated and used as the AF when predicting equivalent field life.


1997 ◽  
Vol 3 (S2) ◽  
pp. 615-616
Author(s):  
P. A. Flinn ◽  
S. Lee ◽  
J. C. Doan ◽  
J. C. Bravman ◽  
T. Marieb ◽  
...  

The passing of current through thin metal lines results in the formation of voids which will eventually cause the line to fail electrically. Gathering of experimental data on electromigration has been limited by two facts: The dimensions of the metal lines on modern integrated circuits are on the order of the resolution limit of light microscopy; and voids in these lines behave quite differently when they are surrounded by a protective film of SiO2 or other dielectric. This dielectric protects the metal surface and constrains the line, pushing back on the metal displaced by void formation. Several additional factors further complicate experimental analysis: the sample test current must be precisely controlled during observation; the sample must be accurately heated to several hundred degrees; the metal lines must be long and narrow (typically 0.2-3.0 (am wide by 300 μm long); testing is often lengthy, sometimes extending over several days even under conditions selected to minimize the time to failure; and electromigration failures are characterized by long incubation periods during which no changes are observed followed by rapid and complex behavior.


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