Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling

2003 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Ed Widener ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Case Studies ◽  
Failure Mode ◽  
Failure Mechanisms ◽  
Physical Analysis ◽  
Certification Programs ◽  
Current Voltage ◽  
Electrical Analysis ◽  
Cell Defect

Abstract Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.

Case Studies of IR Based Rapid PC Motherboard Failure Analysis

2002 ◽  
Author(s):  
Jan Swart ◽  
John Woo ◽  
Randall Zumwalt ◽  
Jeff Birdsley ◽  
Yitages Taffese
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
End Of Life ◽  
Case Studies ◽  
Discovery Process ◽  
Ir Thermography ◽  
Ir Camera ◽  
Manufacturing Defects ◽  
Time Consumption ◽  
Functional Components

Abstract This article discusses the techniques useful in the failure discovery process in PC motherboard. It discusses the application of infrared (IR) camera in failure analysis, which overcomes time consumption problems. The article focuses on the experience gained from nine different case studies, where IR thermography system was used to both measure relative temperatures as well as absolute temperatures of components. The failures investigated are overdriven components, finding end-of-life but still functional components, correctly specified components with quality defects, incorrect component placement, internal voltage common collector to ground low resistance integrated circuits failures, PCB defects resulting in power to ground failures, soldering defects resulting in lead opens or solder bridges, and copper trace manufacturing defects or stress-induced cracks.

Functional Failure Analysis by Induced Stimulus

2002 ◽  
Author(s):  
Jim Colvin
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Deep Submicron ◽  
Thermal Gradients ◽  
Small Signal ◽  
Fault Testing ◽  
Analysis Techniques ◽  
Leakage Path ◽  
Design Deficiencies ◽  
External Stimuli

Abstract In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or e-beam to induce a parametric shift which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. RIL (Resistive Interconnect Localization) is a newer technique which can identify via anomalies functionally using induced thermal gradients to the metal but does not address how to uniformly inject the thermal energy required in the silicon to analyze timing design deficiencies and other defects.[1] With SIFT (Stimulus Induced Fault Testing), numerous stimuli will be used to identify speed, fault, and parametric differences in silicon. The heart of this technique revolves around intentionally disturbing devices with external stimuli and comparing the test criteria to reference parts or timing/voltage sensitivities. Synchronous interfacing is possible to any tester without any wiring or program changes.

Two Unique Case Studies Performed With Photoemission Microscopy (PEM)

1996 ◽  
Author(s):  
G.F. Shade
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Current Flow ◽  
Failure Mechanisms ◽  
Analysis Time ◽  
Unique Case ◽  
Qualitative Evidence ◽  
Leakage Path

Abstract Two cases are presented where photoemission microscopy (PEM) quickly reduced the analysis time by providing qualitative evidence of the suspected failure mechanisms. In both cases, the failures were delaying product shipments and the PEM technique was a "last hope" approach where other proposals were either not successful, or were not available to the analysts. In case one, package residue caused a leakage path that was located and confirmed by PEM. The second case required the use of PEM to observe uniformity of current flow within a polysilicon region. This second analysis provided absolute evidence that the current flow was nonuniform which supported the suspected failure mechanism. It is believed that this is the first reported observation of these two emission mechanisms during a failure analysis.

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

2011 ◽  
Vol 11 (4) ◽  
pp. 302-308
Author(s):  
Sunk-Won Kim ◽  
Hyong-Min Lee ◽  
Hyun-Joong Lee ◽  
Jong-Kwan Woo ◽  
Jun-Ho Cheon ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Deep Submicron ◽  
Cmos Integrated Circuits ◽  
Analysis Technique ◽  
Submicron Cmos

Laser Voltage Imaging: New Perspective Using Second Harmonic Detection on Submicron Technology

2012 ◽  
Author(s):  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Thierry Parrassin ◽  
Michel Vallet ◽  
Philippe Perdu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Case Studies ◽  
Second Harmonic ◽  
New Approach ◽  
Voltage Imaging ◽  
Signal Degradation ◽  
New Perspective ◽  
Process Issue ◽  
The Impact

Abstract The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.

Laser Voltage Probing in Failure Analysis of Advanced Integrated Circuits on SOI

2012 ◽  
Author(s):  
V.K. Ravikumar ◽  
R. Wampler ◽  
M.Y. Ho ◽  
J. Christensen ◽  
S.L. Phoa
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Case Studies ◽  
Timing Analysis ◽  
Fault Isolation ◽  
Root Cause ◽  
Root Cause Identification

Abstract Laser voltage probing is the newest generation of tools that perform timing analysis for electrical fault isolation in advanced failure analysis facilities. This paper uses failure analysis case studies on SOI to showcase the implementation of laser voltage probing in the failure analysis flow and highlight its significance in root-cause identification.

Failure Analysis for Inter-Level Short in Nanometer Semiconductor Technologies

2018 ◽  
Author(s):  
Zhigang Song
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Process Variation ◽  
Failure Mechanisms ◽  
Semiconductor Technology ◽  
New Materials ◽  
Analysis Methodology ◽  
Scaling Down ◽  
Nanometer Regime

Abstract As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.

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