Evaluating High-Level Program Invariants Using Reconfigurable Hardware

Nowadays, highly portable and low-energy computing environments require programming applications able to satisfy computing time and energy constraints. Furthermore, collaborative filtering based recommender systems are intelligent systems that use large databases and perform extensive matrix arithmetic calculations. In this research, we present an optimized algorithm and a parallel hardware implementation as good approach for running embedded collaborative filtering applications. To this end, we have considered high-level synthesis programming for reconfigurable hardware technology. The design was tested under environments where usual parameters and real-world datasets were applied, and compared to usual microprocessors running similar implementations. The performance results obtained by the different implementations were analyzed in computing time and energy consumption terms. The main conclusion is that the optimized algorithm is competitive in embedded applications when considering large datasets and parallel implementations based on reconfigurable hardware.

Download Full-text

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

Journal of Electrical and Computer Engineering ◽

10.1155/2012/484962 ◽

2012 ◽

Vol 2012 ◽

pp. 1-11 ◽

Cited By ~ 10

Author(s):

Ghislain Roquier ◽

Endri Bezati ◽

Marco Mattavelli

Keyword(s):

Programming Model ◽

Multicore Processors ◽

Heterogeneous Systems ◽

Reconfigurable Hardware ◽

Design Flow ◽

Parallel Applications ◽

Application Development ◽

Software Synthesis ◽

Heterogeneous Platforms ◽

High Level

The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities. However, one obstacle for exploiting all the promises of such platforms is deeply rooted in sequential thinking. The sequential programming model does not naturally expose potential parallelism that effectively permits to build parallel applications that can be efficiently mapped on different kind of platforms. A shift of paradigm is necessary at all levels of application development to yield portable and scalable implementations on the widest range of heterogeneous platforms. This paper presents a design flow for the hardware and software synthesis of heterogeneous systems allowing to automatically generate hardware and software components as well as appropriate interfaces, from a unique high-level description of the application, based on the dataflow paradigm, running onto heterogeneous architectures composed by reconfigurable hardware units and multicore processors. Experimental results based on the implementation of several video coding algorithms onto heterogeneous platforms are also provided to show the effectiveness of the approach both in terms of portability and scalability.

Download Full-text

Design and implementation of a high-level image processing machine using reconfigurable hardware

10.1117/12.327017 ◽

1998 ◽

Author(s):

Paul Donachy ◽

Danny Crookes ◽

Ahmed Bouridane ◽

K. Alotaibi ◽

Abdsamad Benkrid

Keyword(s):

Image Processing ◽

Reconfigurable Hardware ◽

Design And Implementation ◽

Processing Machine ◽

High Level

Download Full-text

High level synthesis - reconfigurable hardware implementation of programmable logic controller

IFAC Proceedings Volumes ◽

10.1016/s1474-6670(17)30173-8 ◽

2006 ◽

Vol 39 (21) ◽

pp. 138-143 ◽

Cited By ~ 2

Author(s):

Adam Milik

Keyword(s):

Hardware Implementation ◽

Programmable Logic Controller ◽

Reconfigurable Hardware ◽

High Level Synthesis ◽

Programmable Logic ◽

High Level

Download Full-text

A Novel FPGA-Based Intent Recognition System Utilizing Deep Recurrent Neural Networks

Electronics ◽

10.3390/electronics10202495 ◽

2021 ◽

Vol 10 (20) ◽

pp. 2495

Author(s):

Kyriaki Tsantikidou ◽

Nikolaos Tampouratzis ◽

Ioannis Papaefstathiou

Keyword(s):

Neural Network ◽

Quality Of Life ◽

Recurrent Neural Networks ◽

Recognition System ◽

Reconfigurable Hardware ◽

High Level Synthesis ◽

Intent Recognition ◽

High Level ◽

And Control

In recent years, systems that monitor and control home environments, based on non-vocal and non-manual interfaces, have been introduced to improve the quality of life of people with mobility difficulties. In this work, we present the reconfigurable implementation and optimization of such a novel system that utilizes a recurrent neural network (RNN). As demonstrated in the real-world results, FPGAs have proved to be very efficient when implementing RNNs. In particular, our reconfigurable implementation is more than 150× faster than a high-end Intel Xeon CPU executing the reference inference tasks. Moreover, the proposed system achieves more than 300× the improvements, in terms of energy efficiency, when compared with the server CPU, while, in terms of the reported achieved GFLOPS/W, it outperforms even a server-tailored GPU. An additional important contribution of the work discussed in this study is that the implementation and optimization process demonstrated can also act as a reference to anyone implementing the inference tasks of RNNs in reconfigurable hardware; this is further facilitated by the fact that our C++ code, which is tailored for a high-level-synthesis (HLS) tool, is distributed in open-source, and can easily be incorporated to existing HLS libraries.

Download Full-text