Towards Metric-Driven, Application-Specific Visualization of Attack Graphs

2016 ◽  
pp. 117-134
Author(s):  
Mickael Emirkanian-Bouchard ◽  
Lingyu Wang
Keyword(s):  
Attack Graphs ◽  
Application Specific

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips

2012 ◽  
Vol E95-C (4) ◽  
pp. 534-545 ◽  
Author(s):  
Wei ZHONG ◽  
Takeshi YOSHIMURA ◽  
Bei YU ◽  
Song CHEN ◽  
Sheqin DONG ◽  
...  
Keyword(s):  
Cluster Generation ◽  
Application Specific ◽  
Network Component

Two Formal Analysis of Attack Graphs

2010 ◽  
Vol 21 (4) ◽  
pp. 838-848 ◽  
Author(s):  
Feng CHEN ◽  
Yi ZHANG ◽  
Jin-Shu SU ◽  
Wen-Bao HAN
Keyword(s):  
Formal Analysis ◽  
Attack Graphs

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals Behavioral and Game-Theoretic Security Investments in Interdependent Systems Modeled by Attack Graphs

2020 ◽  
Vol 7 (4) ◽  
pp. 1585-1596 ◽  
Author(s):  
Mustafa Abdallah ◽  
Parinaz Naghizadeh ◽  
Ashish R. Hota ◽  
Timothy Cason ◽  
Saurabh Bagchi ◽  
...  
Keyword(s):  
Attack Graphs ◽  
Game Theoretic ◽  
Security Investments
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