A Compositional Approach for Equivalence Checking of Sequential Circuits with Unknown Reset State and Overlapping Partitions

Author(s):  
Gabriel P. Bischoff ◽  
Karl S. Brace ◽  
Gianpiero Cabodi
2011 ◽  
Vol 204-210 ◽  
pp. 251-254
Author(s):  
Yu Wan Gu ◽  
Guo Dong Shi ◽  
Shi Yan Xie ◽  
Yu Qiang Sun

A parallel checking method is proposed in the paper, in order to improve the speed of sequential circuit checking. The graph form of sequential circuits is isomorphic to finite state machine; a parallel sequential circuit equivalence checking method is designed using parallel minimization method of finite state machine. At last, the effectiveness and feasibility of the method is proved with an instance.


Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.


2019 ◽  
Vol 6 (1) ◽  
pp. 87-129
Author(s):  
Catherine Losada

The latter part of the 1950s saw a major change in Boulez's compositional approach: Instead of creating extensive pre-compositional sketches, he increasingly reused previously composed materials as the basis for new works. The shifting aesthetics that characterized this period had a significant influence on Boulez. His works from the late 1950s explore the ideas of mobility embedded in the open work. Balancing the concept of mobility with the ideals of control that form the basis of his compositional ideology led to an economy of means and an associated emphasis on the concept of development in his compositional process. Both facilitated the creation of new works from a more limited array of base materials.<br/> Tracing the concept of development in a sample of Boulez's sketches and works from the late 1950s through the 1960s, this essay presents a preliminary typology of recurring pitch and temporal developmental techniques. By taking a bird's-eye view, I add an additional level of interpretation, emphasizing their formal function, association with aspects of middleground structure and studying their implications in terms of perception. In this way, I present a new perspective on the association between these techniques and the practice of derivation from a limited amount of material that characterizes these works.


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