Design of a Novel Radix-2 Floating-Point FFT Processor Based on FPGA

2011 ◽  
pp. 609-615 ◽  
Author(s):  
Zhengyan Liu ◽  
Enrang Zheng ◽  
Lingkun Ma
Keyword(s):  
Floating Point ◽  
Fft Processor

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

Integration ◽  
2019 ◽  
Vol 66 ◽  
pp. 164-172
Author(s):  
Xing Wei ◽  
Haigang Yang ◽  
Wei Li ◽  
Zhihong Huang ◽  
Tao Yin ◽  
...  
Keyword(s):  
Binary Tree ◽  
Tree Decomposition ◽  
Floating Point ◽  
Processor Design ◽  
Power Efficient ◽  
Design And Implementation ◽  
Fft Processor

A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

2013 ◽  
Vol 811 ◽  
pp. 441-446
Author(s):  
Jun Ding ◽  
Na Li
Keyword(s):  
Fourier Transform ◽  
High Speed ◽  
Complex Multiplication ◽  
Floating Point ◽  
System Throughput ◽  
Cordic Algorithm ◽  
Clock Frequency ◽  
Sample Number ◽  
Fft Processor ◽  
Dual Core

This paper presents a dual-core floating point FFT processor design based on CORDIC algorithm, enabling high-speed floating-point real-time FFT computation, and its time complexity is (N / 4) Log (N / 2). The design unifiesthe floating complex multiplication and the evaluationof twiddle factors into an iteration, which not only reduces the complexity of complex multiplication but also reduces the difficulty when the butterfly unit deals with floating-point in fast Fourier transform. The butterfly unit unaffected by the size of external memory can handle the Fourier transform with high sample number, both having wider handling range and high handling precision. It uses two logical cores and pipeline technology to improve overall system throughput, with simple hardware structure and system stability.At the end, it does the post-simulation on the Altera chip EP2C35F672C6, and its timing simulation can be run properly under the 50 MHz clock frequency.

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

scholarly journals Novel FPGA-based pipelined floating point FFT processor

2010 ◽  
Vol 7 (4) ◽  
pp. 268-272
Author(s):  
Li Wei ◽  
Wang Jun
Keyword(s):  
Floating Point ◽  
Fft Processor
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