scholarly journals Reliable Contracts for Unreliable Half-Duplex Communications

Author(s):  
Étienne Lozes ◽  
Jules Villard
Keyword(s):  
2010 ◽  
Vol E93-C (6) ◽  
pp. 842-848
Author(s):  
Takushi HASHIDA ◽  
Makoto NAGATA

Author(s):  
Kui Xu ◽  
Ming Zhang ◽  
Jie Liu ◽  
Nan Sha ◽  
Wei Xie ◽  
...  

Abstract In this paper, we design the simultaneous wireless information and power transfer (SWIPT) protocol for massive multi-input multi-output (mMIMO) system with non-linear energy-harvesting (EH) terminals. In this system, the base station (BS) serves a set of uplink fixed half-duplex (HD) terminals with non-linear energy harvester. Considering the non-linearity of practical energy-harvesting circuits, we adopt the realistic non-linear EH model rather than the idealistic linear EH model. The proposed SWIPT protocol can be divided into two phases. The first phase is designed for terminals EH and downlink training. A beam domain energy beamforming method is employed for the wireless power transmission. In the second phase, the BS forms the two-layer receive beamformers for the reception of signals transmitted by terminals. In order to improve the spectral efficiency (SE) of the system, the BS transmit power- and time-switching ratios are optimized. Simulation results show the superiority of the proposed beam-domain SWIPT protocol on SE performance compared with the conventional mMIMO SWIPT protocols.


IEEE Access ◽  
2017 ◽  
Vol 5 ◽  
pp. 7737-7745 ◽  
Author(s):  
Yurong Wang ◽  
Kui Xu ◽  
Aijun Liu ◽  
Xiaochen Xia
Keyword(s):  

2011 ◽  
Vol 383-390 ◽  
pp. 6840-6845 ◽  
Author(s):  
Yong Hong Gu ◽  
Wei Huang ◽  
Qiao Li Yang

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.


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