The UML Diagram to VHDL Code Transformation Based on MDA Methodology

2013 ◽  
pp. 496-503
Author(s):  
Chi-Pan Hwang ◽  
Mu-Song Chen
Keyword(s):  
Code Transformation ◽  
Vhdl Code

DESAIN DAN SIMULASI PERANGKAT KERAS MULTIOPERAND MSB-FIRST ADDER BILANGAN BERTANDA MENGGUNAKAN VHDL

e-NARODROID ◽  
2015 ◽  
Vol 1 (1) ◽  
Author(s):  
Arief Budijanto
Keyword(s):  
Intermediate Result ◽  
Msb First ◽  
Vhdl Code

Msb-First Adder merupakan metode penjumlahan bilangan bulat yang dilakukan mulai dari bobot bit yang paling signifikan terlebih dahulu atau dari bit paling kiri menuju kekanan. Metode pemjumlahan ini mempunyai kelebihan jika proses penjumlahan dibatasi oleh waktu (deadline), karena yang dijumlahkan terlebih dahulu adalah bit yang mempunyai bobot paling signifikan. Selain itu metoda ini juga menunjukan kinerja yang lebih baik ketika digunakan untuk menjumlahkan bilangan banyak (multioperand). Dalam penelitian ini dibuat suatu arsitektur MSB-First Adder yang diaplikasikan untuk komputasi Transformasi Fourier Diskrit (TFD). Tahapan yang dilakukan dalam peneltian ini adalah desain diagram blok arsitektur MSB-First Adder dan Arsitektur TFD yang menggunakan MSBFirst Adder, kemudian memodelkan dalam bentuk VHDL Code . Tahapan yang terakhir yaitu melakukan verifikasi dan analisis dari hasil komputasi TFD yang menggunakan MSB-First adder dibandingkan dengan TFD menggunakan LSB-First Adder dan MATLAB. Hasil akhir komputasi TFD Multioperand MSB-First dengan TFD LSB-First memperlihatkan hasil yang sama. Selain itu pada komputasi TFD Multioperand MSB-First tersedianya hasil-antara (intermediate-result) pada awal proses yang mendekati hasil akhirnya. Hasil ini tidak terjadi pada komputasi prosesor DFT LSB-First. Waktu yang dibutuhkan untuk proses komputasi TFD Multioperand MSB-First adalah 158,506 µS, sedangkan TFD LSB-First adalah 55,308 µS. Agar waktu komputasi TFD Multioperand MSB-First akan mendekati sama dengan waktu komputasi TFD LSB-First, jika pada bagian output memory (RAM dan ROM) dirubah menjadi 16 saluran output (tiap saluran 16 bit) dan multiply nya disusun paralel sebanyak 16 buah.Kata kunci: MSB-First Adder, LSB-First Adder, Hasil-Antara, VHDL, TFD

scholarly journals Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1589
Author(s):  
Krzysztof Kołek ◽  
Andrzej Firlit ◽  
Krzysztof Piątek ◽  
Krzysztof Chmielowiec
Keyword(s):  
Code Generation ◽  
State Of The Art ◽  
Power Grids ◽  
Practical Implementation ◽  
System A ◽  
Measuring Devices ◽  
Point Representation ◽  
Measurement Algorithm ◽  
On Chip ◽  
Vhdl Code

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

I-DMAC: An Intelligent DMA Controller for Utilization - Aware Video Streaming used in AI Applications

2021 ◽  
pp. 60-70
Author(s):  
Piyush Kumar Shukla ◽  
◽  
Prashant Kumar Shukla ◽  
Keyword(s):  
Video Processing ◽  
High Performance ◽  
Data Transfer ◽  
Direct Memory Access ◽  
Large Data ◽  
Video Frame ◽  
Microprocessor System ◽  
Bulk Data ◽  
Xilinx Fpga ◽  
Vhdl Code

The interpretation of large data streams necessitates high-performance repeated transfers, which overload Microprocessor System on Chips (SoC). The effective direct memory access (DMA) controller performs bulk data transfers without the CPU's involvement. The Direct Memory Controller (DMAC) solves this by facilitating bulk data transfer and execution. In this work, we created an intelligent DMAC (I-DMAC) for accessing video processing data without using CPUs. The model includes Bus selection Module, User control signal, Status Register, DMA supported Address, and AXI-PCI subsystems for improved video frame analysis. These modules are experimentally verified in Xilinx FPGA SoC architecture using VHDL code simulation and results compared to the E-DMAC model.

Chopper-controlled PMDC motor drive using VHDL code

2009 ◽  
Author(s):  
Marcelo F. Castoldi ◽  
Gabriel R. C. Dias ◽  
Manoel L. Aguiar ◽  
Valentin O. Roda
Keyword(s):  
Motor Drive ◽  
Vhdl Code

scholarly journals Continuous Delivery of Blockchain Distributed Applications

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 128
Author(s):  
Tomasz Górski
Keyword(s):  
Unified Modeling Language ◽  
Electricity Consumption ◽  
Distributed Applications ◽  
Code Transformation ◽  
Network Nodes ◽  
Unified Modeling ◽  
Distributed Ledger ◽  
Business Application ◽  
Continuous Delivery ◽  
Execution Environment

Ensuring a production-ready state of the application under development is the imminent feature of the Continuous Delivery (CD) approach. In a blockchain network, nodes communicate and store data in a distributed manner. Each node executes the same business application but operates in a distinct execution environment. The literature lacks research focusing on continuous practices for blockchain and Distributed Ledger Technology (DLT). Specifically, it lacks such works with support for both design and deployment. The author has proposed a solution that takes into account the continuous delivery of a business application to diverse deployment environments in the DLT network. As a result, two continuous delivery pipelines have been implemented using the Jenkins automation server. The first pipeline prepares a business application whereas the second one generates complete node deployment packages. As a result, the framework ensures the deployment package in the actual version of the business application with the node-specific up-to-date version of deployment configuration files. The Smart Contract Design Pattern has been used when building a business application. The modeling aspect of blockchain network installation has required using Unified Modeling Language (UML) and the UML Profile for Distributed Ledger Deployment. The refined model-to-code transformation generates deployment configurations for nodes. Both the business application and deployment configurations are stored in the GitHub repositories. For the sake of verification, tests have been conducted for the electricity consumption and supply management system designed for prosumers of renewable energy.

An Integrated Process for Aspect Mining and Refactoring

2010 ◽  
pp. 176-194
Author(s):  
Esteban S. Abait ◽  
Santiago A. Vidal ◽  
Claudia A. Marcos ◽  
Sandra I. Casas ◽  
Albert A. Osiris Sofia
Keyword(s):  
Real System ◽  
The Other ◽  
Inference Rules ◽  
Integrated Process ◽  
Code Transformation ◽  
Aspect Mining ◽  
Crosscutting Concerns ◽  
Whole Process ◽  
Crosscutting Concern ◽  
Object Oriented Systems

Aspect-Oriented Software Development (AOSD) aims at solving the problem of encapsulating crosscutting concerns, which orthogonally crosscut the components of a system, in units called aspects. This encapsulation improves the modularization of a system and in consequence its maintenance and evolution. In this work, the authors propose a systematic process for the migration of object-oriented systems to aspect-oriented ones. This migration is achieved in two main phases: crosscutting concern identification (aspect mining) and code transformation (aspect refactoring). The aspect mining phase is based on dynamic analysis and association rules to identify potential crosscutting concerns. The aspect refactoring phase, on the other hand, uses inference rules to identify the refactoring that can be applied. The whole process is described and its application on a real system is assessed.

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