Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-642-45073-0_8 ◽

2013 ◽

pp. 144-161

Author(s):

Anelise Kologeski ◽

Caroline Concatto ◽

Fernanda Lima Kastensmidt ◽

Luigi Carro

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Power Constraints ◽

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Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

Journal of Systems Architecture ◽

10.1016/j.sysarc.2021.102026 ◽

2021 ◽

Vol 116 ◽

pp. 102026

Author(s):

P. Veda Bhanu ◽

Soumya J.

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Application Mapping ◽

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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081674 ◽

2011 ◽

Author(s):

Zhiliang Qian ◽

Ying Fei Teh ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

Chip Design ◽

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Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2012.6322894 ◽

2012 ◽

Author(s):

Anup Das ◽

Akash Kumar ◽

Bharadwaj Veeravalli

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Network Interface ◽

On Chip ◽

Spatial Division Multiplexing

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A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip

2018 11th International Workshop on Network on Chip Architectures (NoCArc) ◽

10.1109/nocarc.2018.8541212 ◽

2018 ◽

Author(s):

Pieter Stroobant ◽

Sergi Abadal ◽

Wouter Tavernier ◽

Eduard Alarcon ◽

Didier Colle ◽

...

Keyword(s):

Routing Protocol ◽

Fault Tolerant ◽

Network On Chip ◽

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Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-32-9767-8_37 ◽

2019 ◽

pp. 442-454

Author(s):

P. Veda Bhanu ◽

Pranav V. Kulkarni ◽

Sai Pranavi Avadhanam ◽

J. Soumya ◽

Linga Reddy Cenkeramaddi

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Reconfigurable Architecture ◽

Chip Design ◽

Mesh Topology ◽

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Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization

2019 14th Conference on Industrial and Information Systems (ICIIS) ◽

10.1109/iciis47346.2019.9063339 ◽

2019 ◽

Author(s):

P. Veda Bhanu ◽

J. Soumya

Keyword(s):

Particle Swarm Optimization ◽

Fault Tolerant ◽

Particle Swarm ◽

Network On Chip ◽

Discrete Particle Swarm Optimization ◽

Chip Design ◽

Swarm Optimization ◽

Discrete Particle ◽

On Chip ◽

Application Specific

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Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 ◽

10.1145/1366110.1366184 ◽

2008 ◽

Author(s):

Xianfang Tan ◽

Lei Zhang ◽

Shankar Neelkrishnan ◽

Mei Yang ◽

Yingtao Jiang ◽

...

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Chip Design ◽

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Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/tpds.2016.2588482 ◽

2017 ◽

Vol 28 (3) ◽

pp. 838-849 ◽

Author(s):

Yu-Yin Chen ◽

En-Jui Chang ◽

Hsien-Kai Hsin ◽

Kun-Chih Chen ◽

An-Yeu Andy Wu

Keyword(s):

Fault Tolerant ◽

Routing Algorithm ◽

Network On Chip ◽

Path Diversity ◽

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Designing fault-tolerant network-on-chip router architecture

International Journal of Electronics ◽

10.1080/00207217.2010.512016 ◽

2010 ◽

Vol 97 (10) ◽

pp. 1181-1192 ◽

Author(s):

Ashkan Eghbal ◽

Pooria M. Yaghini ◽

H. Pedram ◽

H. R. Zarandi

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Router Architecture ◽

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Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2013.6549806 ◽

2013 ◽

Author(s):

M. Valinataj ◽

P. Liljeberg ◽

J. Plosila

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

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