Design and Simulation of Two Stage Operational Amplifier with Miller Compensation in Nano Regime

Author(s):  
Rohini A. Sarode ◽  
Sanjay S. Chopade
2015 ◽  
Vol 84 (2) ◽  
pp. 173-183 ◽  
Author(s):  
Meysam Akbari ◽  
Masoud Nazari ◽  
Leila Sharifi ◽  
Omid Hashemipour

2014 ◽  
Vol 6 (5) ◽  
pp. 55-66 ◽  
Author(s):  
Fateh Moulahcene ◽  
Nour-Eddine Bouguechal ◽  
Imad Benacer ◽  
Saleh Hanfoug

2019 ◽  
Vol 10 (1) ◽  
pp. 281 ◽  
Author(s):  
Jaesung Kim ◽  
Hyungseup Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm2. The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.


Author(s):  
S. Srinivas Rahul ◽  
◽  
P. Naga Tejaswi ◽  
Y. Mohan Sandeep ◽  
K. Hari Krishna

2013 ◽  
Vol 816-817 ◽  
pp. 1085-1089
Author(s):  
Yu Sen Xu ◽  
Wei Hu ◽  
Feng Ying Huang ◽  
Ji Wei Huang ◽  
Hong Bo She

The objective of this paper is to provide tutorial treatment of the steps for analyzing poles and zeros in multi-stage amplifiers and low dropout (LDO) regulators. The steps can be easily all done by hand simplification without lacking for accuracy, and divided into two methods depending on whether Miller effect exists or not. A two-stage Simple Miller Compensation (SMC) amplifier and an output capacitor-less regulator are analyzed in detail, and several multi-stage amplifiers reported in the literature are also included. To this end, Cadence Spectre simulations are performed to compare hand-computed pole/zero locations with AC analysis.


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