Viterbi Decoder with Configurable Constraint Length with Bit Error Correction for Satellite Communication

<div>Polarization-adjusted convolutional (PAC) codes are special concatenated codes in which we employ a one-to-one convolutional transform as a pre-coding step before the polar transform. In this scheme, the polar transform (as a mapper) and the successive cancellation process (as a demapper) present a synthetic vector channel to the convolutional transformation. The numerical results show that this concatenation improves the Hamming distance properties of polar codes. </div><div>In this work, we implement the parallel list Viterbi algorithm (LVA) and show how the error correction performance moves from the poor performance of the Viterbi algorithm (VA) to the superior performance of list decoding by changing the constraint length, list size, and the sorting strategy (local sorting and global sorting) in the LVA. Also, we analyze the latency of the local sorting of the paths in LVA relative to the global sorting in the list decoding and the trade-off between the sorting latency and the error correction performance.</div>

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Verilog based efficient convolution encoder and viterbi decoder

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v8.i1.pp75-80 ◽

2019 ◽

Vol 8 (1) ◽

pp. 75

Author(s):

Md. Abdul Rawoof ◽

Umasankar Ch. ◽

D. Naresh Kumar ◽

D. Khalandar Basha ◽

N. Madhur

Keyword(s):

Error Correction ◽

Communication Systems ◽

Viterbi Algorithm ◽

Data Communication ◽

Vital Role ◽

Redundant Information ◽

Viterbi Decoder ◽

Correction Technique ◽

Source Data ◽

Digital Communication Systems

In the<strong><em> </em></strong>today’s<strong><em> </em></strong>digital communication Systems,<strong><em> </em></strong>transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

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List Viterbi Decoding of PAC Codes

10.36227/techrxiv.12619706.v2 ◽

2021 ◽

Author(s):

Mohammad Rowshan ◽

Emanuele Viterbo

Keyword(s):

Error Correction ◽

Viterbi Algorithm ◽

Hamming Distance ◽

Poor Performance ◽

Superior Performance ◽

List Decoding ◽

Viterbi Decoding ◽

Vector Channel ◽

Constraint Length ◽

List Viterbi Algorithm

<div>Polarization-adjusted convolutional (PAC) codes are special concatenated codes in which we employ a one-to-one convolutional transform as a pre-coding step before the polar transform. In this scheme, the polar transform (as a mapper) and the successive cancellation process (as a demapper) present a synthetic vector channel to the convolutional transformation. The numerical results show that this concatenation improves the Hamming distance properties of polar codes. </div><div>In this work, we implement the parallel list Viterbi algorithm (LVA) and show how the error correction performance moves from the poor performance of the Viterbi algorithm (VA) to the superior performance of list decoding by changing the constraint length, list size, and the sorting strategy (local sorting and global sorting) in the LVA. Also, we analyze the latency of the local sorting of the paths in LVA relative to the global sorting in the list decoding and the trade-off between the sorting latency and the error correction performance.</div>

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A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

Journal of Applied Research and Technology ◽

10.22201/icat.16656423.2005.3.02.550 ◽

2005 ◽

Vol 3 (02) ◽

Author(s):

E. Garda ◽

M. Guzmán ◽

D. Torres

Keyword(s):

Large Scale ◽

Convolutional Codes ◽

Viterbi Decoder ◽

Single Chip ◽

Description Language ◽

Large Scale Integration ◽

Constraint Length ◽

Hardware Description ◽

Scale Integration ◽

Convolutional Encoder

This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

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Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

International Journal of Computer Applications ◽

10.5120/14550-2638 ◽

2013 ◽

Vol 84 (2) ◽

pp. 24-27

Author(s):

A. Mallaiah ◽

K. Lakshmi Narayana ◽

A. Jaya Lakshmi

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Constraint Length

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