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Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
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26
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11
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Published By IEEE
0818675489
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Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564741
◽
1996
◽
Cited By ~ 5
Author(s):
Isshiki
◽
Dai
Keyword(s):
Bit Serial
◽
Design Capture
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A quantitative analysis of processor-programmable logic interface
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564852
◽
1996
◽
Cited By ~ 6
Author(s):
Rajamani
◽
Viswanath
Keyword(s):
Quantitative Analysis
◽
Programmable Logic
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Using MORRPH in an industrial machine vision system
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564738
◽
1996
◽
Cited By ~ 7
Author(s):
King
◽
Drayer
◽
Conners
◽
Araman
Keyword(s):
Machine Vision
◽
Vision System
◽
Machine Vision System
◽
Industrial Machine
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OneChip: an FPGA processor with reconfigurable logic
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564773
◽
1996
◽
Cited By ~ 130
Author(s):
Wittig
◽
Chow
Keyword(s):
Reconfigurable Logic
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Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564821
◽
1996
◽
Cited By ~ 13
Author(s):
Peterson
◽
O'Connor
◽
Athanas
Keyword(s):
C Programs
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RACER: a reconfigurable constraint-length 14 Viterbi decoder
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564746
◽
1996
◽
Cited By ~ 5
Author(s):
Yeh
◽
Feygin
◽
Chow
Keyword(s):
Viterbi Decoder
◽
Constraint Length
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Aizup-a pipelined processor design and implementation on XILINX FPGA chip
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564755
◽
1996
◽
Author(s):
Yamin Li
◽
Wanming Chu
Keyword(s):
Processor Design
◽
Design And Implementation
◽
Fpga Chip
◽
Xilinx Fpga
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Expressing dynamic reconfiguration by partial evaluation
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564830
◽
1996
◽
Cited By ~ 20
Author(s):
Singh
◽
Hogg
◽
McAuley
Keyword(s):
Partial Evaluation
◽
Dynamic Reconfiguration
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A PCI-compatible FPGA-coprocessor for 2D/3D image processing
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564782
◽
1996
◽
Cited By ~ 6
Author(s):
Knittel
Keyword(s):
Image Processing
◽
3D Image
◽
3D Image Processing
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IEEE Symposium on FPGAs for Custom Computing Machines
Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96
◽
10.1109/fpga.1996.564735
◽
1996
◽
Keyword(s):
Computing Machines
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