RACER: a reconfigurable constraint-length 14 Viterbi decoder

1996 ◽  
Author(s):  
Yeh ◽  
Feygin ◽  
Chow
Keyword(s):  
Viterbi Decoder ◽  
Constraint Length

scholarly journals A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

2005 ◽  
Vol 3 (02) ◽  
Author(s):  
E. Garda ◽  
M. Guzmán ◽  
D. Torres
Keyword(s):  
Large Scale ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Single Chip ◽  
Description Language ◽  
Large Scale Integration ◽  
Constraint Length ◽  
Hardware Description ◽  
Scale Integration ◽  
Convolutional Encoder

This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

scholarly journals Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

2013 ◽  
Vol 84 (2) ◽  
pp. 24-27
Author(s):  
A. Mallaiah ◽  
K. Lakshmi Narayana ◽  
A. Jaya Lakshmi
Keyword(s):  
Low Power ◽  
Viterbi Decoder ◽  
Constraint Length

Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems

2021 ◽  
Author(s):  
A Bernard Rayappa ◽  
TVP Sundararajan
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Viterbi Algorithm ◽  
Model Performance ◽  
Cmos Technology ◽  
High Rate ◽  
Viterbi Decoder ◽  
Hardware Complexity ◽  
Large Power ◽  
Constraint Length

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to a large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add-Compare-Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of the Viterbi decoder mainly depends on its efficient implementation of the ACS module, in the literature, several methods are presented for the implementation of ACS for the Viterbi decoder. The methods based on Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer, Shannon’s decomposition circuits, body-biased pseudo-NMOS logic and Quasi Delay Insensitive (QDI) timing model performance is analyzed. The methods are implemented using CMOS technology. In this paper, FinFET and CNTFET-based ACS implementation is performed. From the analysis, it has been found that the Carbon Nanotube-based implementation is better in performance when compared to the CMOS and FinFET technology. The proposed QDI model and retiming circuits for ACS block operate above 1[Formula: see text]GHz with high driving current and low power.

scholarly journals FPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder

2016 ◽  
pp. 126-130
Author(s):  
J. Tulasi ◽  
T.Venkata Lakshmi ◽  
M. Kamaraju
Keyword(s):  
Communication Systems ◽  
Block Codes ◽  
Viterbi Decoder ◽  
Space Communications ◽  
Convolutional Coding ◽  
Coding Scheme ◽  
Alternative Approach ◽  
Constraint Length ◽  
Convolutional Encoder ◽  
Digital Communication Systems

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

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