scholarly journals Design and Implementation of the Turbo Encoder by using Magnitude Comparator in IVS Chip

2021 ◽  
Vol 12 (6) ◽  
pp. 1537-1545
Author(s):  
Kesari Ananda Samhitha, Y. David Solomon Raju
Keyword(s):  
Parallel Computing ◽  
Low Power ◽  
Processing Time ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Chip Size ◽  
Turbo Encoder ◽  
Variant System ◽  
Research Studies

This research studies the concept and application of the Turbo_encoder to be an integrated module in the In-Vehicle Device (IVS) embedded module by using the magnitude comparator. To create the Turbo_encoder Module, the complex PLDS are used. The variants of series and parallel Turbo_encoders are discussed. It is shown that proportional to chip size processing time also increased in the Turbo_encoder parallel computing variant system. The magnitude comparator with parallel computing variant system is implemented in this project. The usage of proposed logic resulted in efficient area and power usage. The architecture construction using Verilog HDL and implementation and simulation are executed in the Xilinx-ise tool. To incorporate the built module, Xilinx Vertex Low Power is used. The Turbo_encoder module on a single programmable computer is planned to be part of the IVS chip.

scholarly journals TESLA GPUs versus MPI with OpenMP for the Forward Modeling of Gravity and Gravity Gradient of Large Prisms Ensemble

2013 ◽  
Vol 2013 ◽  
pp. 1-15 ◽  
Author(s):  
Carlos Couder-Castañeda ◽  
Carlos Ortiz-Alemán ◽  
Mauricio Gabriel Orozco-del-Castillo ◽  
Mauricio Nava-Flores
Keyword(s):  
Parallel Computing ◽  
Graphics Processing Units ◽  
Forward Modeling ◽  
Gravity Gradient ◽  
Constant Density ◽  
Gravitational Fields ◽  
Design And Implementation ◽  
Cuda Technology ◽  
Performance Results ◽  
Graphics Processing

An implementation with the CUDA technology in a single and in several graphics processing units (GPUs) is presented for the calculation of the forward modeling of gravitational fields from a tridimensional volumetric ensemble composed by unitary prisms of constant density. We compared the performance results obtained with the GPUs against a previous version coded in OpenMP with MPI, and we analyzed the results on both platforms. Today, the use of GPUs represents a breakthrough in parallel computing, which has led to the development of several applications with various applications. Nevertheless, in some applications the decomposition of the tasks is not trivial, as can be appreciated in this paper. Unlike a trivial decomposition of the domain, we proposed to decompose the problem by sets of prisms and use different memory spaces per processing CUDA core, avoiding the performance decay as a result of the constant calls to kernels functions which would be needed in a parallelization by observations points. The design and implementation created are the main contributions of this work, because the parallelization scheme implemented is not trivial. The performance results obtained are comparable to those of a small processing cluster.

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

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