Evalutation of Turbo Decoder Performance Through Software Reference Model

Turbo encoder and decoder are two important blocks of long-term evolution (LTE) systems, as they address the data encoding and decoding in a communication system. In recent years, the wireless communication has advanced to suit the user needs. The power optimization can be achieved by proposing early termination of decoding iteration where the number of iterations is made adjustable which stops the decoding as it finishes the process. Clock gating technique is used at the RTL level to avoid the unnecessary clock given to sequential circuits; here clock supplies are a major source of power dissipation. The performance of a system is affected due to the numbers of parameters, including channel noise, type of decoding and encoding techniques, type of interleaver, number of iterations, and frame length on the Matlab Simulink platform. A software reference model for turbo encoder and decoder are modeled using MATLAB Simulink. Performance of the proposed model is estimated and analyzed on various parameters like frame length, number of iterations, and channel noise.

A Watermark Approach for Image Transmission: Implementation of Channel Coding Technique with Security

In this paper an approach for secured digital image transmission with watermark is being proposed. The tremendous growth in technology for various applications demand secured communications across the wireless channels. Secured image transmission is the one of the prominent process in digital communication applications. A watermark is embedded in to the image data that is to be protected from unauthorized users. The cryptographic algorithms chosen for secured transmission led to the need for hardware implementation. In the process of secured image transmission turbo encoder is proposed for error correction. The proposed approach is realized in terms of hardware for the digital logic size, area and power consumption using Xilinx 14.2 software. Synthesizing and implementation of verilog code on the target device xc6slx150-2fgg484 for timing constraints, device utilization and performance details. © 2020 Elsevier Ltd. All rights reserved. Selection and/or Peer-review under responsibility of International Conference on Mechanical, Electronics and Computer Engineering

Design and Implementation of the Turbo Encoder by using Magnitude Comparator in IVS Chip

This research studies the concept and application of the Turbo_encoder to be an integrated module in the In-Vehicle Device (IVS) embedded module by using the magnitude comparator. To create the Turbo_encoder Module, the complex PLDS are used. The variants of series and parallel Turbo_encoders are discussed. It is shown that proportional to chip size processing time also increased in the Turbo_encoder parallel computing variant system. The magnitude comparator with parallel computing variant system is implemented in this project. The usage of proposed logic resulted in efficient area and power usage. The architecture construction using Verilog HDL and implementation and simulation are executed in the Xilinx-ise tool. To incorporate the built module, Xilinx Vertex Low Power is used. The Turbo_encoder module on a single programmable computer is planned to be part of the IVS chip.

Error Detection in Turbo Decoding using Neural Network

In this paper reduction of errors in turbo decoding is done using neural network. Turbo codes was one of the first thriving attempt for obtaining error correcting performance in the vicinity of the theoretical Shannon bound of –1.6 db. Parallel concatenated encoding and iterative decoding are the two techniques available for constructing turbo codes. Decrease in Eb/No necessary to get a desired bit-error rate (BER) is achieved for every iteration in turbo decoding. But the improvement in Eb/No decreases for each iteration. From the turbo encoder, the output is taken and this is added with noise, when transmitting through the channel. The noisy data is fed as an input to the neural network. The neural network is trained for getting the desired target. The desired target is the encoded data. The turbo decoder decodes the output of neural network. The neural network help to reduce the number of errors. Bit error rate of turbo decoder trained using neural network is less than the bit error rate of turbo decoder without training.

Evolution of Wireless Communication along with Encoders

Now a days technology drastically increasing, leads to increase in communication also. Internet of Things (IOT) is very basic fundamental necessary to the consumers in this decade, which requires a communication path mainly from end to end. By understanding this technology growth, took as motivation and started a survey for turbo decoder architecture in Long Term Evolution (LTE) and 3GPP-LTE communication. Different generation technologies adopt different kinds of encoder as well as decoder to encrypt the data which can be sent from source devices to destination devices, which consists parameters like data rate, frequency used to transmit and speed of transitioning i.e., encoding and decoding the data at the transmitter as well as receiver. This paper represents a survey on different architectures of turbo decoder in LTE communication which can give a brief idea about the communication and also the usage of turbo encoder in various applications. Initially we look back a history and development of a communication system till LTE. Later we discuss the different technologies and topologies on turbo decoder along with its architecture, advantage and disadvantage.

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

Interleaver is an indispensable component in the design of Turbo encoder and Turbo Decoder. QPP interleaver is a 3GPP specified conflict free interleaver for turbo channel coding scheme for all code block sizes of 40 to 6144. Thus the efficient design of a conflict free reconfigurable QPP interleaver for turbo encoder and turbo decoder is a pre-eminent task in turbo channel coding scheme. In this article, Design of a simplified reconfigurable (40 to 6144 block sizes) Recursive QPP interleaver for computation of address locations to minimize the computational complexity and to avoid storage of interleaver tables has been presented. The proposed interleaver will be further integrated in the design and implementation of high throughput parallel turbo decoder. The proposed design is synthesized and implemented using 28nm CMOS technology Zynq Zed FPGA and achieved low processing timing constraints, utilization and power constraints compared with other conventional designs.

Turbo-Space Time Block Coded and Turbo-Vertical Bell Laboratories Layered Space Time coded Wireless Communication: Which One is better to Use and under What Circumstances?

In this research, performance of Turbo-Space Time Block Coded and Turbo-Vertical Bell Laboratories Layered Space Time coded Multiple Input Multiple Output Wireless Communication System is compared and investigated to find which one is better under which circumstances. The Turbo Encoder accepts binary bits as input and generates turbo encoded bits as output which is sent to 64 QAM modulator. These 64 QAM Modulated symbols are further mapped using Space Time Block Code and Vertical Bell Laboratories Layered Space Time code for Turbo-Space Time Block Coded system and Turbo-Vertical Bell Laboratories Layered Space Time coded system respectively and then divided into several streams based on number of transmit antennas before transmission. It is found that there is 3 to 22 dB coding gain at 10-5 for using Turbo-STBC instead of using Turbo-VBLAST for 2 or 3 or 4 transmit antennas and 2 or 3 or 4 or 5 or 6 receive antennas. On the other hand, at low SNR STBC shows 1-2 b/s/Hz improvement in capacity compare to VBLAST but capacity declines significantly at high SNR for using STBC. It is also observed that VBLAST improves the capacity around 5 to 15 b/s/Hz at high SNR.

High performance turbo encoder using mealy FSM state encoding technique

Error-correction Coding plays a vital role to obtain efficient and high quality data transmission, in today’s high speed wireless communication system. Considering the requirement of using high data rates by Long Term Evolution (LTE) system, parallel concatenation of two convolutional encoders were used to design turbo encoder. In this research task a high speed turbo encoder, which is a key component in the transmitter of wireless communication System, with memory based interleaver has been designed and implemented on FPGA for 3rd Generation Partnership Project (3GPP) defined Long Term Evolution – Advanced (LTE-A) standard using Finite state Machine(FSM) encoding technique. Memory based quadratic permutation polynomial (QPP) interleaver shuffles a sequence of binary data and supports any of the 188 block sizes from N= 40 to N= 6144. The proposed turbo encoder is implemented using 28nm CMOS technology and achieved 300 Mbps data rate by using 1% of available total hardware logic. By using the proposed technique, encoded data can be released continuously with the help of two parallel memories to write/read the input using pipelining concept.