scholarly journals A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Thilo Pionteck ◽  
Roman Koch ◽  
Carsten Albrecht ◽  
Erik Maehle

Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.

2022 ◽  
Vol 18 (2) ◽  
pp. 1-22
Author(s):  
João Paulo Cardoso de Lima ◽  
Marcelo Brandalero ◽  
Michael Hübner ◽  
Luigi Carro

Accelerating finite-state automata benefits several emerging application domains that are built on pattern matching. In-memory architectures, such as the Automata Processor (AP), are efficient to speed them up, at least for outperforming traditional von-Neumann architectures. In spite of the AP’s massive parallelism, current APs suffer from poor memory density, inefficient routing architectures, and limited capabilities. Although these limitations can be lessened by emerging memory technologies, its architecture is still the major source of huge communication demands and lack of scalability. To address these issues, we present STAP , a Scalable TCAM-based architecture for Automata Processing . STAP adopts a reconfigurable array of processing elements, which are based on memristive Ternary CAMs (TCAMs), to efficiently implement Non-deterministic finite automata (NFAs) through proper encoding and mapping methods. The CAD tool for STAP integrates the design flow of automata applications, a specific mapping algorithm, and place and route tools for connecting processing elements by RRAM-based programmable interconnects. Results showed 1.47× higher throughput when processing 16-bit input symbols, and improvements of 3.9× and 25× on state and routing densities over the state-of-the-art AP, while preserving 10 4 programming cycles.


Author(s):  
Maryam Hammami ◽  
Hatem Bellaaj

The Cloud storage is the most important issue today. This is due to a rapidly changing needs and a huge mass of varied and important data to back up. In this paper, we describe a work in progress and propose a flexible system architecture for data storage in the Cloud. This system is centered on the Data Manager module. This module provides various functions such as the dispersion of data in fragments, encryption and storage of fragments... etc. This architecture proves to be very relevant. It ensures consistency between different components. On the other hand, it ensures the security and availability of data.


2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Heechun Park ◽  
Bon Woong Ku ◽  
Kyungwook Chang ◽  
Da Eun Shim ◽  
Sung Kyu Lim

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.


2016 ◽  
Author(s):  
Carmen Pastor ◽  
Willem Jellema ◽  
Pablo Zuluaga-Ramírez ◽  
David Arrazola ◽  
M. Fernández-Rodriguez ◽  
...  

Author(s):  
Cari R. Bryant ◽  
Matt Bohm ◽  
Robert B. Stone ◽  
Daniel A. McAdams

This paper builds on previous concept generation techniques explored at the University of Missouri - Rolla and presents an interactive concept generation tool aimed specifically at the early concept generation phase of the design process. Research into automated concept generation design theories led to the creation of two distinct design tools: an automated morphological search that presents a designer with a static matrix of solutions that solve the desired input functionality and a computational concept generation algorithm that presents a designer with a static list of compatible component chains that solve the desired input functionality. The merger of both the automated morphological matrix and concept generation algorithm yields an interactive concept generator that allows the user to select specific solution components while receiving instantaneous feedback on component compatibility. The research presented evaluates the conceptual results from the hybrid morphological matrix approach and compares interactively constructed solutions to those returned by the non-interactive automated morphological matrix generator using a dog food sample packet counter as a case study.


Author(s):  
Gary A. Gabriele ◽  
Agustî Maria I. Serrano

Abstract The need for superior design tools has lead to the development of better and more complex computer aided design programs. Two of the more important new developments in application tools being investigation are Object Oriented Languages, and HyperMedia. Object Oriented Languages allow the development of CAD tools where the parts being designed and the design procedures specified are conceptualized as objects. This allows for the development of design aids that are non-procedural and more readily manipulated by the user trying to accomplish a design task. HyperMedia allows for the easy inclusion of many different types of data, such as design charts and graphs, into the tool that are normally difficult to include in design tools programmed with more conventional programming languages. This paper explores the development of a computer aided design tool for the design of a single stage gear box using the development HyperCard® environment and the HyperTalk® programming language. The resulting program provides a user friendly interface, the ability to handle several kinds of design information including graphic and textual, and a non-procedural design tool to help the user design simple, one stage gear boxes. Help facilities in the program make it suitable for undergraduate instruction in a machine elements design course.


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