Architecture and Design Flow Optimizations for Power-Aware FPGAs

2006 ◽  
pp. 20-1-20-15
Author(s):  
N Vijaykrishnan ◽  
Aman Gayasen
Keyword(s):  
Design Flow ◽  
Architecture And Design

scholarly journals A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Thilo Pionteck ◽  
Roman Koch ◽  
Carsten Albrecht ◽  
Erik Maehle
Keyword(s):  
System Architecture ◽  
Design Tool ◽  
Design Flow ◽  
Design Tools ◽  
System Architectures ◽  
Flexible System ◽  
Reconfigurable System ◽  
Communication Needs ◽  
On Chip ◽  
Architecture And Design

Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.

Architecture and Design Flow for a Highly Efficient Structured ASIC

2013 ◽  
Vol 21 (3) ◽  
pp. 424-433 ◽  
Author(s):  
Man-Ho Ho ◽  
Yan-Qing Ai ◽  
Thomas Chun-Pong Chau ◽  
Steve C. L. Yuen ◽  
Chiu-Sing Choy ◽  
...  
Keyword(s):  
Design Flow ◽  
Highly Efficient ◽  
Architecture And Design

HPDP: Architecture and design flow: High performance data processor

2017 ◽  
Author(s):  
Olga Dokianaki ◽  
Volker Baumgarte ◽  
Mohsin Syed ◽  
Constantin Papadas ◽  
Tim Helfers ◽  
...  
Keyword(s):  
High Performance ◽  
Performance Data ◽  
Design Flow ◽  
Data Processor ◽  
Architecture And Design

STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs

2022 ◽  
Vol 18 (2) ◽  
pp. 1-22
Author(s):  
João Paulo Cardoso de Lima ◽  
Marcelo Brandalero ◽  
Michael Hübner ◽  
Luigi Carro
Keyword(s):  
Finite Automata ◽  
Design Tool ◽  
Design Flow ◽  
Von Neumann ◽  
Mapping Algorithm ◽  
Processing Elements ◽  
Finite State ◽  
Specific Mapping ◽  
Architecture And Design ◽  
Communication Demands

Accelerating finite-state automata benefits several emerging application domains that are built on pattern matching. In-memory architectures, such as the Automata Processor (AP), are efficient to speed them up, at least for outperforming traditional von-Neumann architectures. In spite of the AP’s massive parallelism, current APs suffer from poor memory density, inefficient routing architectures, and limited capabilities. Although these limitations can be lessened by emerging memory technologies, its architecture is still the major source of huge communication demands and lack of scalability. To address these issues, we present STAP , a Scalable TCAM-based architecture for Automata Processing . STAP adopts a reconfigurable array of processing elements, which are based on memristive Ternary CAMs (TCAMs), to efficiently implement Non-deterministic finite automata (NFAs) through proper encoding and mapping methods. The CAD tool for STAP integrates the design flow of automata applications, a specific mapping algorithm, and place and route tools for connecting processing elements by RRAM-based programmable interconnects. Results showed 1.47× higher throughput when processing 16-bit input symbols, and improvements of 3.9× and 25× on state and routing densities over the state-of-the-art AP, while preserving 10 4 programming cycles.

FPGA Architecture and Design Flow

2021 ◽  
pp. 367-383
Author(s):  
Vaibbhav Taraate
Keyword(s):  
Design Flow ◽  
Fpga Architecture ◽  
Architecture And Design
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