Performance Analysis of Reversible Logic-Based Full Adder Using BSIM4 Model

2019 ◽  
pp. 659-665
Author(s):  
Shivani Horke ◽  
Manisha Waje ◽  
Rupali Patil
Keyword(s):  
Performance Analysis ◽  
Full Adder ◽  
Reversible Logic

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

Performance Analysis of 1 Bit Full Adder Circuits for 45 nm Technology

2018 ◽  
Vol 13 (1) ◽  
pp. 88-92
Author(s):  
Vipin Kumar Shrivas ◽  
Ravi Yadav ◽  
Indra Vijay Singh
Keyword(s):  
Performance Analysis ◽  
Full Adder

scholarly journals Design and Performasnce Analysis of Hybrid Full Adder Using Finfet 40nm Technology

2019 ◽  
Vol 8 (6) ◽  
pp. 4521-4525
Keyword(s):  
Performance Analysis ◽  
Energy Efficient ◽  
Full Adder ◽  
Propagation Delay ◽  
Leakage Power ◽  
Drive Current ◽  
Internal Logic ◽  
Low Leakage ◽  
Cadence Tool ◽  
Power And Energy

Designing a low power and energy efficient circuits in FinFET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and FinFETs for designing the hybrid adder cells. At transistor level, CMOS and FinFET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm FinFET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.

Design and Performance Analysis of All-Optical Reversible Full Adder, as ALU

2019 ◽  
Vol 90 (5) ◽  
pp. 899-909
Author(s):  
Kamal K. Upadhyay ◽  
Saumya Srivastava ◽  
Vanya Arun ◽  
Narendra Kumar Shukla
Keyword(s):  
Performance Analysis ◽  
Full Adder ◽  
All Optical ◽  
And Performance
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