An instruction set for reversible Turing machines

2021 ◽  
Vol 58 (4) ◽  
pp. 377-396
Author(s):  
Kenichi Morita
1994 ◽  
Vol 05 (03n04) ◽  
pp. 231-246
Author(s):  
JERRY L. TRAHAN ◽  
SUNDARARAJAN VEDANTHAM

The log cost measure has been viewed as a more reasonable method of measuring the time complexity of an algorithm than the unit cost measure. The more widely used unit cost measure becomes unrealistic if the algorithm handles extremely large integers. Parallel machines have not been examined under the log cost measure. In this paper, we investigate the Parallel Random Access Machine under the log cost measure. Let the instruction set of a basic PRAM include addition, subtraction, and Boolean operations. We relate resource-bounded complexity classes of log cost PRAMs to complexity classes of Turing machines and circuits. We also relate log cost PRAMs with different instruction sets by simulations that are much more efficient than possible in the unit cost case. Let LCRCWk(CRCWk) denote the class of languages accepted by a log cost (unit cost) basic CRCW PRAM in O( log k n) time with the polynomial in n number of processors. We position the log cost PRAM in the hierarchy of parallel complexity classes as: ACk=CRCWk⊆(NCk+1, LCRCWk+1)⊆ACk+1=CRCWk+1.


2020 ◽  
Author(s):  
Widya Sri Utami

Perangkat keras komputer adalah semua bagian fisik komputer, dandibedakan dengan data yang berada di dalamnya atau yang beroperasi didalamnya, dan dibedakan dengan perangkat lunak (software) yang menyediakaninstruksi untuk perangkat keras dalam menyelesaikan tugasnya. Hardware dalam bahasa Indonesia disebut juga dengan nama “perangkatkeras” yaitu salah satu komponen dari sebuah komputer yang sifat alatnya bisa dilihat dan diraba secara langsung atau yang berbentuk nyata, yang berfungsiuntuk mendukung proses komputerisasi. Hardware dapat bekerja berdasarkan perintah yang telah ditentukan atau disebut juga dengan istilah “instruction set”. Adanya perintah yang dapat dimengerti oleh hardware, maka hardware tersebutdapat melakukan berbagai kegiatan yang telah ditentukan oleh pemberi perintah.


2020 ◽  
Author(s):  
Alzena Ritonga

Perangkat keras komputer adalah semua bagian fisik komputer, dan dibedakan dengan datayang berbeda di dalamnya atau yang beroperasi di dalamnya, dan dibedakan dengan perangkat lunak ( software) yang menyediakan instruksi untuk perangkat keras dalam menyelesaikan tugasnya. Hardware dalam bahasa Indonesia disebut juga dengan nama " Perangkat keras " Yaitu salah satu komponen dari sebuah komputer yang sifat alatnya bisa dilihat dan dapat di raba secara langsung atau yang berbentuk nyata, yang berfungsi untuk mendukung proses komputerisasi. Hardware dapat bekerja berdasarkan perintah yang telah ditentukan atau disebut juga dengan istilah " Instruction set". Adanya perintah yang dapat dimengerti oleh hardware,, maka hardware tersebut dapat melakukan berbagai kegiatan yang telah ditentukan oleh pemberi perintah. Secara fisik, komputer terdiri dari dari beberapa komponen yang merupakan suatu sistem. Sistem adalah komponen- komponen yang saling bekerja sama membentuk suatu kesatuan. Apabila salah satu komponen tidak berfungsi, akan mengakibatkan tidak berfungsi nya proses proses yang ada dalam komputer dengan baik. Komponen komputer ini termasuk dalam kategori elemen perangkat keras ( hardware). Berdasarkan fungsinya, perangkat keras komputer dibagi menjadi:input device ( unit masukan) ; proses device ( unit pemrosesan) ; output device ( unit keluaran) ; backing storage ( unit penyimpanan) ; dan Porifera( unit tambahan).


Author(s):  
Raymundo Morado ◽  
Francisco Hernández-Quiroz

Turing machines as a model of intelligence can be motivated under some assumptions, both mathematical and philosophical. Some of these are about the possibility, the necessity, and the limits of representing problem solving by mechanical means. The assumptions about representation that we consider in this paper are related to information representability and availability, processing as solving, nonessentiality of complexity issues, and finiteness, discreteness and sequentiality of the representation. We discuss these assumptions and particularly something that might happen if they were to be rejected or weakened. Tinkering with these assumptions sheds light on the import of alternative computational models.


2018 ◽  
Author(s):  
Rajendra K. Bera

It now appears that quantum computers are poised to enter the world of computing and establish its dominance, especially, in the cloud. Turing machines (classical computers) tied to the laws of classical physics will not vanish from our lives but begin to play a subordinate role to quantum computers tied to the enigmatic laws of quantum physics that deal with such non-intuitive phenomena as superposition, entanglement, collapse of the wave function, and teleportation, all occurring in Hilbert space. The aim of this 3-part paper is to introduce the readers to a core set of quantum algorithms based on the postulates of quantum mechanics, and reveal the amazing power of quantum computing.


2012 ◽  
Vol 35 (7) ◽  
pp. 1407 ◽  
Author(s):  
Yong-Ming LI ◽  
Ping LI

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.


2020 ◽  
Vol 46 (6) ◽  
pp. 428-432
Author(s):  
S. S. Marchenkov ◽  
S. D. Makeev
Keyword(s):  

1992 ◽  
Vol 44 (2) ◽  
pp. 272-286 ◽  
Author(s):  
Johannes Kobler ◽  
Uwe Schïng ◽  
Seinosuke Toda ◽  
Jacobo Torán
Keyword(s):  

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