Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture

2021 ◽  
Author(s):  
Rajkumar Sarma ◽  
Cherry Bhargava ◽  
Shruti Jain ◽  
Vikram Kumar Kamboj
Keyword(s):  
Low Power ◽  
Floating Point

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics

2021 ◽  
pp. 1-1
Author(s):  
Fabio Montagna ◽  
Stefan Mach ◽  
Simone Benatti ◽  
Angelo Garofalo ◽  
Gianmarco Ottavi ◽  
...  
Keyword(s):  
Low Power ◽  
Data Analytics ◽  
Sensor Data ◽  
Floating Point

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

2016 ◽  
Vol 5 (2) ◽  
pp. 118
Author(s):  
J. Vijay Kumar ◽  
B. Naga Raju ◽  
M. Vasu Babu ◽  
T. Ramanjappa
Keyword(s):  
Low Power ◽  
Arithmetic Operation ◽  
Floating Point ◽  
Double Precision ◽  
Verilog Hdl ◽  
Logical Function ◽  
Floating Point Arithmetic ◽  
Risc Processor ◽  
Operation Results ◽  
Point Arithmetic

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device.  The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support

2009 ◽  
Vol 58 (2) ◽  
pp. 175-187 ◽  
Author(s):  
Dimitri Tan ◽  
Carl E. Lemonds ◽  
Michael J. Schulte
Keyword(s):  
Low Power ◽  
Floating Point ◽  
Multiple Precision
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