A novel split capacitor array switching scheme with proportional coefficient for SAR ADC

2018 ◽  
Vol 98 (3) ◽  
pp. 597-605 ◽  
Author(s):  
Ruixue Ding ◽  
Shaopeng Dong ◽  
Shubin Liu ◽  
Depeng Sun ◽  
Zhangming Zhu
Keyword(s):  
Sar Adc ◽  
Switching Scheme ◽  
Capacitor Array ◽  
Split Capacitor

scholarly journals Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  
Keyword(s):  
High Speed ◽  
Average Power ◽  
Sar Adc ◽  
Capacitor Array ◽  
Medium Resolution ◽  
Charge Recycling ◽  
Split Capacitor ◽  
Array Structure ◽  
Conversion Performance ◽  
Binary Weighted

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC

2019 ◽  
Vol 28 (13) ◽  
pp. 1930010 ◽  
Author(s):  
Shubin Liu ◽  
Haolin Han ◽  
Ruixue Ding
Keyword(s):  
Successive Approximation ◽  
Energy Efficient ◽  
Sar Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Capacitor Array ◽  
Asymmetric Capacitor ◽  
Conventional Scheme

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

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