scholarly journals Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  
Keyword(s):  
High Speed ◽  
Average Power ◽  
Sar Adc ◽  
Capacitor Array ◽  
Medium Resolution ◽  
Charge Recycling ◽  
Split Capacitor ◽  
Array Structure ◽  
Conversion Performance ◽  
Binary Weighted

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

Linearity analysis on a series-split capacitor array for high-speed SAR ADCs

2008 ◽  
Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  
Keyword(s):  
High Speed ◽  
Capacitor Array ◽  
Split Capacitor

A novel split capacitor array switching scheme with proportional coefficient for SAR ADC

2018 ◽  
Vol 98 (3) ◽  
pp. 597-605 ◽  
Author(s):  
Ruixue Ding ◽  
Shaopeng Dong ◽  
Shubin Liu ◽  
Depeng Sun ◽  
Zhangming Zhu
Keyword(s):  
Sar Adc ◽  
Switching Scheme ◽  
Capacitor Array ◽  
Split Capacitor

scholarly journals A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

2021 ◽  
Vol 15 ◽  
pp. 556-568
Author(s):  
Chaya Shetty ◽  
M. Nagabushanam ◽  
Venkatesh Nuthan Prasad
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Sar Adc ◽  
Cmos Process ◽  
Digital To Analog Converter ◽  
Additional Advantage ◽  
Analog To Digital ◽  
Split Capacitor

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

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