A W-band CMOS down-conversion mixer using CMOS-inverter-based RF GM stage for conversion gain and linearity enhancement

2019 ◽  
Vol 99 (1) ◽  
pp. 133-146 ◽  
Author(s):  
Yo-Sheng Lin ◽  
Kai-Siang Lan
2017 ◽  
Vol 93 (1) ◽  
pp. 49-59 ◽  
Author(s):  
Yo-Sheng Lin ◽  
Ming-Huang Kao ◽  
Hou-Ru Pan ◽  
Kai-Siang Lan

2014 ◽  
Vol 24 (01) ◽  
pp. 1550002 ◽  
Author(s):  
Mina Amiri ◽  
Adib Abrishamifar

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.


2016 ◽  
Vol 8 (4-5) ◽  
pp. 703-712
Author(s):  
Xin Yang ◽  
Xiao Xu ◽  
Takayuki Shibata ◽  
Toshihiko Yoshimasu

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.


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