Design exploration of a NVM based hybrid instruction memory organization for embedded platforms

2013 ◽  
Vol 17 (3-4) ◽  
pp. 459-483 ◽  
Author(s):  
Manu Perumkunnil Komalan ◽  
José Ignacio Gómez Pérez ◽  
Christian Tenllado ◽  
José Miguel Montañana ◽  
Antonio Artés ◽  
...  
Author(s):  
Jon Andoni Duñabeitia ◽  
Manuel Perea ◽  
Manuel Carreiras

One essential issue for models of bilingual memory organization is to what degree the representation from one of the languages is shared with the other language. In this study, we examine whether there is a symmetrical translation priming effect with highly proficient, simultaneous bilinguals. We conducted a masked priming lexical decision experiment with cognate and noncognate translation equivalents. Results showed a significant masked translation priming effect for both cognates and noncognates, with a greater priming effect for cognates. Furthermore, the magnitude of the translation priming was similar in the two directions. Thus, highly fluent bilinguals do develop symmetrical between-language links, as predicted by the Revised Hierarchical model and the BIA+ model. We examine the implications of these results for models of bilingual memory.


Author(s):  
Lukas Gressl ◽  
Alexander Rech ◽  
Christian Steger ◽  
Andreas Sinnhofer ◽  
Ralph Weissnegger
Keyword(s):  

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4805
Author(s):  
Saad Abbasi ◽  
Mahmoud Famouri ◽  
Mohammad Javad Shafiee ◽  
Alexander Wong

Human operators often diagnose industrial machinery via anomalous sounds. Given the new advances in the field of machine learning, automated acoustic anomaly detection can lead to reliable maintenance of machinery. However, deep learning-driven anomaly detection methods often require an extensive amount of computational resources prohibiting their deployment in factories. Here we explore a machine-driven design exploration strategy to create OutlierNets, a family of highly compact deep convolutional autoencoder network architectures featuring as few as 686 parameters, model sizes as small as 2.7 KB, and as low as 2.8 million FLOPs, with a detection accuracy matching or exceeding published architectures with as many as 4 million parameters. The architectures are deployed on an Intel Core i5 as well as a ARM Cortex A72 to assess performance on hardware that is likely to be used in industry. Experimental results on the model’s latency show that the OutlierNet architectures can achieve as much as 30x lower latency than published networks.


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