Optimization of Test Wrapper for TSV Based 3D SOCs

2016 ◽  
Vol 32 (5) ◽  
pp. 511-529 ◽  
Author(s):  
Surajit Kumar Roy ◽  
Chandan Giri ◽  
Hafizur Rahaman
Keyword(s):  
2013 ◽  
Vol 6 (2) ◽  
pp. 10-14
Author(s):  
Aijun Zhu ◽  
◽  
Zhi Li ◽  
Wangchun Zhu ◽  
Chuanpei Xu ◽  
...  

2013 ◽  
Vol 12 (24) ◽  
pp. 8242-8248
Author(s):  
Zhang Ying ◽  
Wu Ning ◽  
Ge Fen ◽  
Chen Xin
Keyword(s):  

2017 ◽  
Vol 14 (1) ◽  
pp. 511-516
Author(s):  
Sharmila Durai ◽  
Rangarajan Parthasarathy

System-on-chip (SoC) face major problem due to vulnerability of hack. The hacker target the cryptographic IP block in the architecture of SoC. However, PUF test wrapper provides the security for individual IP core. The individual IP core protection plays major problem in PUF test. We propose a novel method to protect the IP core with QFT-PUF authentication mechanism. QFT-PUF implement in PSOC-FPGA. The mechanism reduces the area and memory in architecture. The proposed method of key generation and their handling process drive from Quantum Fourier Transform. From the validation of QFT-PUF, Fault Acceptance Rate (FAR) increases then the Fault Rejection Rate (FRR).


Author(s):  
Sergey Mikhtonyuk ◽  
Maksim Davydov ◽  
Roman Hwang ◽  
Dmitry Shcherbin

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