TSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip

The 3D System-on-chip (SoC) technology supports the vertical interconnectivity required for the purpose of functional, supply and test access purposes through the use of Through Silicon Vias (TSVs). Little number of available TSVs for test purpose necessitates the optimization of test infrastructure. This paper proposes an algorithm to design the test wrapper for the 3D cores such that the number of the TSVs used per TAM chain are minimized. Test time optimization is done by balancing the lengths of the individual Wrapper chain inside the core. The proposed heuristic firstly distributes the different core elements on the given TAM chains and then uses a diagraph for their insertion ordering to get minimum possible TSV utilization. Simulation results are presented for the different cores of the ITC’02 SoC benchmark circuits. Results show that TSVs can be reduced to 20-30 percent with around 60-70 percent reduction in CPU time utilization for heavy SoCs in comparison to the other proposed techniques.

Real Time Implementation of QFT-PUF Architecture for Data Secure System-on-Chip

System-on-chip (SoC) face major problem due to vulnerability of hack. The hacker target the cryptographic IP block in the architecture of SoC. However, PUF test wrapper provides the security for individual IP core. The individual IP core protection plays major problem in PUF test. We propose a novel method to protect the IP core with QFT-PUF authentication mechanism. QFT-PUF implement in PSOC-FPGA. The mechanism reduces the area and memory in architecture. The proposed method of key generation and their handling process drive from Quantum Fourier Transform. From the validation of QFT-PUF, Fault Acceptance Rate (FAR) increases then the Fault Rejection Rate (FRR).