This paper presents the power-optimized third-order Cascaded Integrator Comb (CIC) Filter for the DeltaSigma (Δ-∑) Analog-to-Digital Converter (ADC). The CIC Filter refers to a type of decimation filter used in ADC to remove quantization error caused by the modulator. It also occupies less area, when compared to other decimation filter, due to the absence of multiplier. In Δ-∑ ADC, the power consumption is mainly driven by the decimation filter. Hence, careful optimization of the decimation filter is necessary to design an ADC with low power. In this paper, the True Single Phase Clocked (TSPC) D-Flip Flop, which is made up of split-output latches, was applied as the register, instead of conventional D-Flip Flops. The proposed design displayed a significant reduction in power consumption. The proposed architecture was realized by using the CMOS 0.13µm technology. At 256kHz of sampling rate, the CIC Filter only consumed 47.99µW power. The supply voltage used at 1.5V and 13-bit of resolution had been achieved by using 32 oversampling ratio. The layout for 1-bit third-order CIC Filter was also realized with the size of 105.580 × 29.930µm2 .
Keywords: Δ-∑ Analog to Digital Converter, Decimation Filter, Cascaded Integrator Comb, Integrator, Differentiator
1 MHz sampling rate 12-bit low-power analog-to-digital converter for data processing in particle detectors