Sampling Rate Optimization for Improving the Cascaded Integrator Comb Filter Characteristics

The cascaded integrator comb (CIC) filters are characterized by coefficient less and reduced hardware requirement, which make them an economical finite impulse response (FIR) class in many signal processing applications. They consist of an integrator section working at the high sampling rate and a comb section working at the low sampling rate. However, they don’t have well defined frequency response. To remedy this problem, several structures have been proposed but the performance is still unsatisfactory. Thence, this paper deals with the improvement of the CIC filter characteristics by optimizing its sampling rate. This solution increases the performance characteristics of CIC filters by improving the stopband attenuation and ripple as well as the passband droop. Also, this paper presents a comparison of the proposed method with some other existing structures such as the conventional CIC, the sharpened CIC, and the modified sharpened CIC filters, which has proven the effectiveness of the proposed method.

Performance analysis of CIC multirate filter in cognitive radio for efficient pulse shaping in wireless domain

<span>In this paper, the Performance Analysis of Cascade Integrator Comb Filter in context of Filter Bank Multicarrier Transmission has been presented for Cognitive radio. A benefit of the chosen technique is that, a CIC filter can be designed with a slight adjustment in parameters of interest. The entire performance of the filters designed is analyzed and evaluated by analyzing Normalized Amplitude versus Normalized Frequency plots at typical K and N values. The roll off factor plays a significant role in performance analysis of CIC filter. The results shown are a useful advance for rf design engineers working in the domain of multirate signal processing in wireless communication. To ensure the acceptable performance of Enhanced FBMC, computational complexity, and transmission burst length need to be reduced. The effect of Stop band attenuation on the edges of Magnitude and Frequency responses has been studied under constraints such as Lp, K and M during different simulation runs</span>.

FPGA Based Performance Analysis of Multistage CIC Decimation Filter Design with former CIC Filter for WiMAX Applications

The motto of this paper is to design and realize decimation filter using CIC filter. The main drawback of this filter is there is large droop in pass band and very less attenuation in stop band. So, to improve the frequency response of CIC filter we go for two stage realization of CIC filter. At the initial stage we use CIC filter and in the last stage we use Kaiser Window and improve the characteristics of filter design. When we design a filter using multistage methodology the order of the filter as well as power also decreases. Tools used are MATLAB Simulink Model and Xilinx system generator and realization is done on Virtex V-XC5VLX110T-3ff136. In this paper the proposed two stage realization is compared with respect to two stages Kaiser window realization in the terms of number of LUT’s required, slices as well as power dissipation and improvements in frequency response with respect to conventional CIC filter are compared

PERFORMANCE ANALYSIS OF FULL ADDERS IN CIC DECIMATION FILTER

This article presents analysis of various full adder architecture on Cascaded Integrator-Comb (CIC) filter of delta-sigma ADC. The structure of CIC filter consists of an integrator and a differentiator stage that is built from a cascaded full adder and delay element. Since each of the element within CIC filter has its own low-power architecture, full adder is one of the block that consumes huge amount of power compared to others. In this paper, four different type of full adder’s architecture is designed and simulated with CIC decimation filter. There are 28T conventional, pseudo-NMOS adder, 16T hybrid adder and modified 14T hybrid adder. The performance parameters such as delay, total power dissipation and power delay product (PDP) of CIC filter were compared. This analysis shows that 16T hybrid full adder CIC filter has reduced up to 38.15% of power consumption and 39.18% of power product delay compared to conventional adder. Hence, a complete 1-bit third order of 16T hybrid adder CIC filter is implemented with size area of 118.23µm × 22.38µm. Keywords: Delta-sigma ADC, Low-power, CIC decimation filter, Full adder

LOW POWER CIC FILTER DESIGN FOR DELTA SIGMA ADC

This paper presents the power-optimized third-order Cascaded Integrator Comb (CIC) Filter for the DeltaSigma (Δ-∑) Analog-to-Digital Converter (ADC). The CIC Filter refers to a type of decimation filter used in ADC to remove quantization error caused by the modulator. It also occupies less area, when compared to other decimation filter, due to the absence of multiplier. In Δ-∑ ADC, the power consumption is mainly driven by the decimation filter. Hence, careful optimization of the decimation filter is necessary to design an ADC with low power. In this paper, the True Single Phase Clocked (TSPC) D-Flip Flop, which is made up of split-output latches, was applied as the register, instead of conventional D-Flip Flops. The proposed design displayed a significant reduction in power consumption. The proposed architecture was realized by using the CMOS 0.13µm technology. At 256kHz of sampling rate, the CIC Filter only consumed 47.99µW power. The supply voltage used at 1.5V and 13-bit of resolution had been achieved by using 32 oversampling ratio. The layout for 1-bit third-order CIC Filter was also realized with the size of 105.580 × 29.930µm2 . Keywords: Δ-∑ Analog to Digital Converter, Decimation Filter, Cascaded Integrator Comb, Integrator, Differentiator