Scalableα-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

2018 ◽  
Vol 83 ◽  
pp. 180-187 ◽  
Author(s):  
Shruti Kalra ◽  
AB Bhattacharyya
Keyword(s):  
Circuit Design ◽  
Power Law ◽  
Integrated Circuit ◽  
Deep Submicron ◽  
Integrated Circuit Design ◽  
Digital Integrated Circuit

Statistical Gate-Delay Modeling with Copulas

2020 ◽  
Vol 15 (3) ◽  
pp. 1-10
Author(s):  
Walter Schneider
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Process Variations ◽  
Deep Submicron ◽  
Experimental Results ◽  
Gate Delay ◽  
Integrated Circuit Design ◽  
Circuit Performance ◽  
Delay Models ◽  
Innovative Concept

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

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