Statistical Gate-Delay Modeling with Copulas
Keyword(s):
The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.
2018 ◽
Vol 83
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pp. 180-187
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1982 ◽
Vol 129
(4)
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pp. 199
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2014 ◽
Vol 134
(5)
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pp. 283-283
Keyword(s):
1992 ◽
Vol 2
(2)
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pp. 147-158
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