Cognitions about time affect perception, behavior, and physiology – A review on effects of external clock-speed manipulations

AbstractI'll describe the current status of the GRAPE-DR project. The GRAPE-DR is the next-generation hardware for N-body simulation. Unlike the previous GRAPE hardwares, it is programmable SIMD machine with a large number of simple processors integrated into a single chip. The GRAPE-DR chip consists of 512 simple processors and operates at the clock speed of 500 MHz, delivering the theoretical peak speed of 512/226 Gflops (single/double precision). As of August 2006, the first prototype board with the sample chip successfully passed the test we prepared. The full GRAPE-DR system will consist of 4096 chips, reaching the theoretical peak speed of 2 Pflops.

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Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

Journal of Circuits System and Computers ◽

10.1142/s0218126617500773 ◽

2017 ◽

Vol 26 (05) ◽

pp. 1750077 ◽

Cited By ~ 1

Author(s):

Anush Bekal ◽

Shabi Tabassum ◽

Manish Goswami

Keyword(s):

Low Power ◽

Successive Approximation ◽

Digital Control ◽

Low Power Design ◽

Cmos Technology ◽

Control Logic ◽

Control Block ◽

Logic Block ◽

External Clock ◽

Asynchronous Sar

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

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Mass-correlated rotational Raman spectra with high resolution, broad bandwidth, and absolute frequency accuracy

Proceedings of the National Academy of Sciences ◽

10.1073/pnas.1721756115 ◽

2018 ◽

Vol 115 (20) ◽

pp. 5072-5076 ◽

Cited By ~ 4

Author(s):

Christian Schröter ◽

Jong Chan Lee ◽

Thomas Schultz

Keyword(s):

Raman Spectra ◽

Optical Excitation ◽

Rotational Transition ◽

Observation Time ◽

Absolute Frequency ◽

Naturally Occurring ◽

Order Of Magnitude ◽

Quantum Wave ◽

External Clock ◽

Time And Energy

We present mass-correlated rotational alignment spectroscopy, based on the optical excitation of a coherent rotational quantum wave and the observation of temporal wave interferences in a mass spectrometer. Combined electronic and opto-mechanical delays increased the observation time and energy resolution by an order of magnitude compared with preceding time-domain measurements. Rotational transition frequencies were referenced to an external clock for accurate absolute frequency measurements. Rotational Raman spectra for six naturally occurring carbon disulfide isotopologues were resolved with 3 MHz resolution over a spectral range of 500 GHz. Rotational constants were determined with single-kilohertz accuracy, competitive with state-of-the-art frequency domain measurements.

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clock speed

Computer Science and Communications Dictionary ◽

10.1007/1-4020-0613-6_2768 ◽

2006 ◽

pp. 219-219

Keyword(s):

Clock Speed

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Integrated DVB-X2 Receiver Architecture with Common Acceleration Engine

Applied Sciences ◽

10.3390/app9193983 ◽

2019 ◽

Vol 9 (19) ◽

pp. 3983

Author(s):

Youn-Sung Lee ◽

Joongjin Kook

Keyword(s):

Entire System ◽

Laboratory Setting ◽

Channel Decoding ◽

Operating Modes ◽

Clock Speed ◽

Receiver Architecture ◽

Technical Issues ◽

Integrated Architecture ◽

Multi Mode ◽

Test Scenarios

This paper proposes an integrated DVB-X2 receiver architecture to support multi-mode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The entire system consists of a tuner block, a H/W-based receiver engine, a frame processor, and an A/V decoder. Specifically, an integrated architecture to solve key design and technical issues such as reducing the complexity of the receiver, efficiently accessing the H/W-based receiver engine, and simplifying an OFDM demodulator is proposed. The H/W-based receiver engine for DVB-X2 demodulation and channel decoding functions is implemented in two FPGA devices. The frame processor is implemented with 256 MB memory and a DSP operating at a clock speed of 1.0 GHz. To verify functionalities of the proposed DVB-X2 receiver, various test scenarios were considered in the laboratory setting. In particular, the proposed system was tested under various operating modes, as specified in standards such as DVB-T2, DVB-C2, and DVB-S2, and demonstrated successful operations in all test scenarios.

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