scholarly journals A visual tool for generating digital calibration certificates (DCCs) in Excel

2021 ◽  
Vol 18 ◽  
pp. 100175
Author(s):  
Dirk Röske
Author(s):  
Federico Ricci ◽  
Giulia Bravo ◽  
Alberto Modenese ◽  
Fabrizio De Pasquale ◽  
Davide Ferrari ◽  
...  

We developed a visual tool to assess risk perception for a sample of male construction workers (forty Italian and twenty-eight immigrant workers), just before and after a sixteen-hour training course. The questionnaire included photographs of real construction sites, and workers were instructed to select pictograms representing the occupational risks present in each photograph. Points were awarded for correctly identifying any risks that were present, and points were deducted for failing to identify risks that were present or identifying risks that were not present. We found: (1) Before the course, risk perception was significantly lower in immigrants compared to Italians ( p < .001); (2) risk perception improved significantly ( p < .001) among all workers tested; and (3) after the training, the difference in risk perception between Italians and immigrants was no longer statistically significant ( p = .1086). Although the sample size was relatively small, the results suggest that the training is effective and may reduce the degree to which cultural and linguistic barriers hinder risk perception. Moreover, the use of images and pictograms instead of words to evaluate risk perception could also be applied to nonconstruction workplaces.


2019 ◽  
Vol 27 (5) ◽  
pp. 1217-1235
Author(s):  
Baltasar García Perez‐Schofield ◽  
Matías García Rivera ◽  
Francisco Ortin ◽  
María J. Lado

Author(s):  
Yungang Wei ◽  
Xiaoran Qin ◽  
Xiaoye Tan ◽  
Xiaohang Yu ◽  
Bo Sun ◽  
...  

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.


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