An LP/CBP reconfigurable analog baseband circuit for software-defined radio receivers in 65nm CMOS

2015 ◽  
Vol 46 (1) ◽  
pp. 81-95 ◽  
Author(s):  
Xinwang Zhang ◽  
Bingqiao Liu ◽  
Zhihua Wang ◽  
Baoyong Chi
2016 ◽  
Vol 87 (11) ◽  
pp. 114706 ◽  
Author(s):  
Teemu Nieminen ◽  
Pasi Lähteenmäki ◽  
Zhenbing Tan ◽  
Daniel Cox ◽  
Pertti J. Hakonen

Author(s):  
Ta Hai Tung

With the development of the computationalpower of programmable processors, the Software-DefinedRadio (SDR) approach for GPS receivers has been widelyconsidered. However, in comparison with the conventionalhardware receivers, the computational speed of the SDRreceivers is still a problem needed to be improved. As afirst process of the digital processing part, and also themost resource consuming process of a GPS receiver, thesignal acquisition process is very important and neededto be improved in order to suit with the SDR approach.This paper introduces a hybrid signal acquisition methodleveraging the conventional serial search acquisition (typical in hardware receivers), and the FFT-based parallelsearch (typical in SDR receivers) in order to significantlyimprove the acquisition sensitivity, meanwhile keep thecomputational complexity still comparable with that of theFFT-based parallel method.


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