Adopting the Verification Methodology Manual’s (VMM) hierarchical structure, this paper presents a design of available verification platform based on System Verilog adopted. The platform completed can implement constrained-random test, directed test, and error stimulus test with high efficiency; moreover, gain maximum code reuse. Using Direct Programming Interface (DPI), the verification platform can conveniently link C++ with the model that realized the function of Design Under Test (DUT), and then to test it. At last the paper shows the experiment results to prove the effectiveness and practicality of the platform by verification sample of HOG chip.