Due to the exponential increase of electronic devices
that are connected to the Internet, the amount of data that they
produce have grown to the same extent. In order to face the
processing of these data, the use of some automatic learning
algorithms, also known as Machine Learning, has become
widespread. The most popular is the one known as neural
networks. These algorithms need a great deal of resources to
compute all their operations, and because of that, they have been
traditionally implemented in application specific integrated
circuits. However, recently there have been a boom in
implementations in field programmable gate arrays, also known
as FPGAs. These allow greater parallelism in the implementation
of the algorithms. Field Programmable Gate Arrays (FPGA)
implementation based feature extraction method is proposed in
this paper. This particular application is handwritten offline digit
recognition. The classification depends on simple 2 layer MultiLayer Perceptron (MLP). The particular feature extraction
approach is suitable for execution of FPGA because it is utilized
with subtraction and addition operations. From Standard
database handwritten digit images of normalized 40×40 pixel the
features are extracted by the proposed method. It has been
discovered by experiential outcomes that 85% accuracy is
achieved by proposed system. Overall, as compared to other
systems, it is less complex, more accurate and simple. Further
this project explains IEE-754 format single precision floating
point MAC unit’s FPGA implementation which is utilized for
feeding the neurons weighted inputs in artificial neural networks.
Data representation range is improved by floating point numbers
utilization to a higher number from smaller number that is highly
suggested for Artificial Neuron Network. The code is developed
in HDL, simulated and synthesis results are extracted using
Xilinx synthesis tools .In order to validate its computational
accuracy of the FFT, an MATLAB validation script is used to
verify the output of HDL with standard reference model.
A hardware implementation of artificial neural networks using field programmable gate arrays
