This paper describes high speed compressors for high speed parallel
multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal
Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for
high speed multiplication. These compressors reduce vertical critical path
more rapidly than conventional compressors. A 5-3 conventional compressor can
take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2
steps. These compressors are simulated with H-Spice at a temperature of 25?C
at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power
Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are
calculated to analyze the total propagation delay and energy consumption. All
the compressors are designed with half adder and full Adders only.