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Time redundancy and gate sizing soft error-tolerant based adder design
Integration
◽
10.1016/j.vlsi.2021.01.001
◽
2021
◽
Vol 78
◽
pp. 49-59
Author(s):
Aiman H. El-Maleh
◽
Ghashmi H. Bin Talib
Keyword(s):
Soft Error
◽
Gate Sizing
◽
Time Redundancy
Download Full-text
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References
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09
◽
10.1145/1629911.1630042
◽
2009
◽
Cited By ~ 14
Author(s):
Weiguang Sheng
◽
Liyi Xiao
◽
Zhigang Mao
Keyword(s):
Genetic Algorithm
◽
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Gate Sizing
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Multi Objective
◽
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Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm
2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
◽
10.1109/iolts.2018.8474275
◽
2018
◽
Author(s):
Xuebing Cao
◽
Liyi Xiao
◽
Linzhe Li
◽
Jie Li
◽
Jiaqiang Li
◽
...
Keyword(s):
Particle Swarm Optimization
◽
Optimization Algorithm
◽
Particle Swarm Optimization Algorithm
◽
Particle Swarm
◽
Soft Error
◽
Gate Sizing
◽
Combinational Circuit
◽
Swarm Optimization
◽
Multi Objective
◽
Error Optimization
Download Full-text
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2008.2003268
◽
2008
◽
Vol 27
(10)
◽
pp. 1788-1797
◽
Cited By ~ 17
Author(s):
F. Dabiri
◽
A. Nahapetian
◽
T. Massey
◽
M. Potkonjak
◽
M. Sarrafzadeh
Keyword(s):
Power Optimization
◽
Soft Error
◽
Gate Sizing
◽
General Methodology
Download Full-text
Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme
IEEE Access
◽
10.1109/access.2019.2902505
◽
2019
◽
Vol 7
◽
pp. 66485-66495
◽
Cited By ~ 3
Author(s):
Mohsen Raji
◽
M. Amin Sabet
◽
Behnam Ghavami
Keyword(s):
Digital Circuits
◽
Soft Error
◽
Gate Sizing
◽
Reliability Improvement
Download Full-text
Soft Error-Aware Power Optimization Using Gate Sizing
Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
◽
10.1007/978-3-540-74442-9_25
◽
2007
◽
pp. 255-267
◽
Cited By ~ 2
Author(s):
Foad Dabiri
◽
Ani Nahapetian
◽
Miodrag Potkonjak
◽
Majid Sarrafzadeh
Keyword(s):
Power Optimization
◽
Soft Error
◽
Gate Sizing
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An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
IEICE Transactions on Electronics
◽
10.1587/transele.e98.c.741
◽
2015
◽
Vol E98.C
(7)
◽
pp. 741-750
Author(s):
Takashi IMAGAWA
◽
Masayuki HIROMOTO
◽
Hiroyuki OCHI
◽
Takashi SATO
Keyword(s):
Error Correction
◽
Soft Error
◽
Error Tolerance
◽
Time Redundancy
◽
Correction Scheme
Download Full-text
Time redundancy based soft-error tolerance to rescue nanometer technologies
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)
◽
10.1109/vtest.1999.766651
◽
2003
◽
Cited By ~ 293
Author(s):
M. Nicolaidis
Keyword(s):
Soft Error
◽
Error Tolerance
◽
Time Redundancy
Download Full-text
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2016.2569562
◽
2017
◽
Vol 25
(1)
◽
pp. 247-260
◽
Cited By ~ 10
Author(s):
Mohsen Raji
◽
Behnam Ghavami
Keyword(s):
Error Rate
◽
Process Variations
◽
Soft Error
◽
Gate Sizing
◽
Combinational Circuits
◽
Rate Reduction
◽
Soft Error Rate
Download Full-text
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08
◽
10.1145/1393921.1393948
◽
2008
◽
Cited By ~ 6
Author(s):
Koustav Bhattacharya
◽
Nagarajan Ranganathan
Keyword(s):
Error Rate
◽
Soft Error
◽
Simultaneous Optimization
◽
Gate Sizing
◽
Soft Error Rate
Download Full-text
Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing
Soft Error Reliability of VLSI Circuits
◽
10.1007/978-3-030-51610-9_6
◽
2020
◽
pp. 75-92
Author(s):
Behnam Ghavami
◽
Mohsen Raji
Keyword(s):
Circuit Design
◽
Soft Error
◽
Gate Sizing
Download Full-text
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