On estimation of noise variance in two-dimensional signal processing

1991 ◽  
Vol 23 (03) ◽  
pp. 476-495 ◽  
Author(s):  
Peter Hall ◽  
J. W. Kay ◽  
D. M. Titterington
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal ◽  
Optimal Selection ◽  
Two Dimensional ◽  
Noise Variance ◽  
Asymptotically Optimal ◽  
Extensive Analysis ◽  
Optimal Configurations ◽  
Selection Of

Estimation of noise variance is an important component of digital signal processing, in particular of image processing. In this paper we develop methods for estimating the variance of white noise in a two-dimensional degraded signal. We discuss optimal configurations of pixels for difference-based estimation, and describe asymptotically optimal selection of weights for the component pixels. After extensive analysis of possible configurations we recommend averaging linear configurations over a variety of different orientations (usually two or four). This approach produces estimators with properties of both statistical and numerical efficiency.

On estimation of noise variance in two-dimensional signal processing

1991 ◽  
Vol 23 (3) ◽  
pp. 476-495 ◽  
Author(s):  
Peter Hall ◽  
J. W. Kay ◽  
D. M. Titterington
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal ◽  
Optimal Selection ◽  
Two Dimensional ◽  
Noise Variance ◽  
Asymptotically Optimal ◽  
Extensive Analysis ◽  
Optimal Configurations ◽  
Selection Of

Estimation of noise variance is an important component of digital signal processing, in particular of image processing. In this paper we develop methods for estimating the variance of white noise in a two-dimensional degraded signal. We discuss optimal configurations of pixels for difference-based estimation, and describe asymptotically optimal selection of weights for the component pixels. After extensive analysis of possible configurations we recommend averaging linear configurations over a variety of different orientations (usually two or four). This approach produces estimators with properties of both statistical and numerical efficiency.

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

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