Multi-functional Logic Circuits Composed of Ultra-thin Electrolyte-gated Transistor with Wafer-scale Integration

Various electrolyte-gated transistors (EGTs) have been widely studied because of their high carrier density, resulting from the formation of a thin electric double layer (EDL). However, most of the electrolytes...

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Creating Novel Transport Properties in Electric Double Layer Field Effect Transistors Based on Layered Materials

MRS Proceedings ◽

10.1557/opl.2011.289 ◽

2011 ◽

Vol 1288 ◽

Cited By ~ 1

Author(s):

J. T. Ye ◽

M. F. Craciun ◽

M. Koshino ◽

S. Russo ◽

Y. Kasahara ◽

...

Keyword(s):

Transport Properties ◽

Double Layer ◽

Electric Double Layer ◽

Carrier Density ◽

Field Effect ◽

Field Effect Transistors ◽

Layered Materials ◽

High Transition ◽

High Carrier ◽

Atomically Flat

ABSTRACTWe present a study on the liquid/solid interface, which can be electrostatically doped to a high carrier density (n~1014 cm-2) by electric-double-layer gating. Using micro-cleavage technique on the layered materials: ZrNCl and graphene, atomically flat channel surfaces can be easily prepared. Intrinsic high carrier density transport regime is accessed at the channel interface of electric double-layer field effect transistor, where novel transport properties are unveiled as the field-induced superconductivity on the ZrNCl with high transition temperature at 15 K, and accessing a high carrier density up to 2×1014 cm-2 in graphene and its multi-layers.

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Wafer scale integration

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1988.0038 ◽

1988 ◽

Vol 135 (6) ◽

pp. 281

Author(s):

J.B. Butcher ◽

K.K. Johnstone

Keyword(s):

Wafer Scale ◽

Wafer Scale Integration ◽

Scale Integration

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AREA EFFICIENT LAYOUT OF BALANCED HYPERCUBES

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156495000237 ◽

1995 ◽

Vol 06 (04) ◽

pp. 631-645 ◽

Cited By ~ 28

Author(s):

KE HUANG ◽

JIE WU

Keyword(s):

Efficient System ◽

Strong Connectivity ◽

Wafer Scale ◽

System Reconfiguration ◽

Faulty Processor ◽

Balanced Hypercube ◽

Wafer Scale Integration ◽

Scale Integration ◽

Area Efficient ◽

Load Balanced

As a multicomputer structure, the balanced hypercube is a variant of the standard hypercube for multicomputers, with desirable properties of strong connectivity, regularity, and symmetry. This structure is a special type of load balanced graph designed to tolerate processor failure. In balanced hypercubes, each processor has a backup (matching) processor that shares the same set of neighboring nodes. Therefore, tasks that run on a faulty processor can be reactivated in the backup processor to provide efficient system reconfiguration. In this paper, we study the implementation of balanced hypercubes in VLSI using the Wafer Scale Integration (VLSI/WSI) technology. Emphasis is on VLSI/WSI layout and area estimates. Our results show that the balanced hypercube can be implemented at least as efficient as the standard hypercube in an area layout and more efficient in a linear layout.

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