An efficient I/sub DDQ/ test generation scheme for bridging faults in CMOS digital circuits

Author(s):  
Tzuhao Chen ◽  
I.N. Hajj ◽  
E.M. Rudnick ◽  
J.H. Patel
VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.


2010 ◽  
Vol 439-440 ◽  
pp. 1235-1240
Author(s):  
Ling Chen ◽  
Zhong Liang Pan

A new test generation method for the bridging faults in digital circuits is proposed in this paper, the method is based on shared binary decision diagram. The shared binary decision diagram can represent many logic functions simultaneously by sharing isomorphic subgraphs, it is used to represent the digital circuits with multiple primary outputs. The binary decision diagram is constructed respectively for the normal circuit and faulty circuit having a bridging fault. The test vectors of the bridging fault can be produced by a XOR operation of the two binary decision diagrams. The experimental results on a lot of benchmark circuits demonstrate that the test method proposed in this paper can get the test vectors of the bridging faults if the faults are testable.


Sign in / Sign up

Export Citation Format

Share Document