Clock signal requirement for high-frequency, high dynamic range acquisition systems

2005 ◽  
Vol 76 (11) ◽  
pp. 115103 ◽  
Author(s):  
Ivo Viščor ◽  
Josef Halámek ◽  
Marco Villa
2000 ◽  
Vol 36 (13) ◽  
pp. 1096 ◽  
Author(s):  
W.C. Song ◽  
C.J. Oh ◽  
G.H. Cho ◽  
H.B. Jung

2010 ◽  
Vol 56 (4) ◽  
pp. 399-404
Author(s):  
Przemysław Rydygier ◽  
Władysław Dąbrowski ◽  
Tomasz Fiutowski ◽  
Piotr Wiącek

Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode ArraysIn the paper we present the design and test results of an integrated circuit combining a sample&hold circuit and an analogue multiplexer. The circuit has been designed as a building block for a multi-channel Application Specific Integrated Circuit (ASIC) for recording signals from alive neuronal tissue using high-density micro-electrode arrays (MEAs). The design is optimised with respect to critical requirements for such applications, i.e. short sampling time, low power dissipation, good linearity and high dynamic range. Presented design comprises sample&hold circuits with class AB operational amplifier, novel shift register, which allows minimising cross-coupling of the clock signal and control logic. The circuit has been designed in 0.35μm CMOS process and has been successfully implemented in a prototype multi-channel ASIC.


1986 ◽  
Vol 133 (1) ◽  
pp. 26
Author(s):  
J. Mellis ◽  
G.R. Adams ◽  
K.D. Ward

2009 ◽  
Vol 35 (2) ◽  
pp. 113-122 ◽  
Author(s):  
Ke-Hu YANG ◽  
Jing JI ◽  
Jian-Jun GUO ◽  
Wen-Sheng YU

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