Calculation of the electron velocity distribution in high electron mobility transistors using an ensemble Monte Carlo method

1985 ◽  
Vol 57 (12) ◽  
pp. 5336-5339 ◽  
Author(s):  
T. Wang ◽  
K. Hess
Coatings ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 318 ◽  
Author(s):  
He Guan ◽  
Shaoxi Wang ◽  
Lingli Chen ◽  
Bo Gao ◽  
Ying Wang ◽  
...  

Because of the high electron mobility and electron velocity in the channel, InAs/AlSb high electron mobility transistors (HEMTs) have excellent physical properties, compared with the other traditional III-V semiconductor components, such as ultra-high cut-off frequency, very low power consumption and good noise performance. In this paper, both the structure and working principle of InAs/AlSb HEMTs were studied, the energy band distribution of the InAs/AlSb heterojunction epitaxy was analyzed, and the generation mechanism and scattering mechanism of two-dimensional electron gas (2DEG) in InAs channel were demonstrated, based on the software simulation in detail. In order to discuss the impact of different epitaxial structures on the 2DEG and electron mobility in channel, four kinds of epitaxies with different thickness of InAs channel and AlSb upper-barrier were manufactured. The samples were evaluated with the contact Hall test. It is found the sample with a channel thickness of 15 nm and upper-barrier layer of 17 nm shows a best compromised sheet carrier concentration of 2.56 × 1012 cm−2 and electron mobility of 1.81 × 104 cm2/V·s, and a low sheet resistivity of 135 Ω/□, which we considered to be the optimized thickness of channel layer and upper-barrier layer. This study is a reference to further design InAs/AlSb HEMT, by ensuring a good device performance.


VLSI Design ◽  
2001 ◽  
Vol 13 (1-4) ◽  
pp. 435-439 ◽  
Author(s):  
K. Kalna ◽  
A. Asenov ◽  
K. Elgaid ◽  
I. Thayne

The effect of scaling into deep decanano dimensions on the performance of pseudomorphic high electron mobility transistors (pHEMTs) is extensively studied using Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and 30nm is performed in both lateral and vertical directions. The devices exhibit a significant improvement in transconductance during scaling, even though external resistances become a limiting factor.


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