scholarly journals Large-Scale and Energy-Efficient Tensorized Optical Neural Networks on III-V-on-Silicon MOSCAP Platform

APL Photonics ◽  
2021 ◽  
Author(s):  
Xian Xiao ◽  
Mehmet Berkay On ◽  
Thomas Van Vaerenbergh ◽  
Di Liang ◽  
Ray Beausoleil ◽  
...  
Keyword(s):  
Neural Networks ◽  
Energy Efficient ◽  
Large Scale ◽  
Optical Neural Networks

scholarly journals Implementation of Pruned Backpropagation Neural Network Based on Photonic Integrated Circuits

Photonics ◽  
2021 ◽  
Vol 8 (9) ◽  
pp. 363
Author(s):  
Qi Zhang ◽  
Zhuangzhuang Xing ◽  
Duan Huang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Integrated Circuits ◽  
Energy Efficient ◽  
High Speed ◽  
Large Scale ◽  
Matrix Operation ◽  
Optical Neural Networks ◽  
Optical Neural Network ◽  
Random Initialization

We demonstrate a pruned high-speed and energy-efficient optical backpropagation (BP) neural network. The micro-ring resonator (MRR) banks, as the core of the weight matrix operation, are used for large-scale weighted summation. We find that tuning a pruned MRR weight banks model gives an equivalent performance in training with the model of random initialization. Results show that the overall accuracy of the optical neural network on the MNIST dataset is 93.49% after pruning six-layer MRR weight banks on the condition of low insertion loss. This work is scalable to much more complex networks, such as convolutional neural networks and recurrent neural networks, and provides a potential guide for truly large-scale optical neural networks.

scholarly journals Large-Scale Optical Neural Networks Based on Photoelectric Multiplication

2019 ◽  
Vol 9 (2) ◽  
Author(s):  
Ryan Hamerly ◽  
Liane Bernstein ◽  
Alexander Sludds ◽  
Marin Soljačić ◽  
Dirk Englund
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Optical Neural Networks

scholarly journals Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

2019 ◽  
Vol 10 (1) ◽  
pp. 1 ◽  
Author(s):  
Fanny Spagnolo ◽  
Stefania Perri ◽  
Fabio Frustaci ◽  
Pasquale Corsonello
Keyword(s):  
Neural Networks ◽  
Embedded System ◽  
Convolutional Neural Networks ◽  
Energy Efficient ◽  
Power Efficiency ◽  
High Performance ◽  
Large Scale ◽  
Low Cost ◽  
Frame Rate ◽  
Field Programmable

Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.

scholarly journals Digital Optical Neural Networks for Large-Scale Machine Learning

2020 ◽  
Author(s):  
Liane Bernstein ◽  
Alexander Sludds ◽  
Ryan Hamerly ◽  
Vivienne Sze ◽  
Joel Emer ◽  
...  
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Large Scale ◽  
Optical Neural Networks

A Developmental Method for Evolving Large-Scale Spiking Neural Networks

2012 ◽  
Vol 35 (12) ◽  
pp. 2633 ◽  
Author(s):  
Xiang-Hong LIN ◽  
Tian-Wen ZHANG ◽  
Gui-Cang ZHANG
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Spiking Neural Networks

Energy efficient biomorphic pulse information coding in electronic neurons for the entrance unit of the neuroprocessor

2019 ◽  
Vol 5 (3) ◽  
pp. 186-212 ◽  
Author(s):  
Alexander D. Pisarev
Keyword(s):  
Neural Networks ◽  
Energy Efficiency ◽  
Energy Efficient ◽  
Information Transfer ◽  
Biological Systems ◽  
Technological Parameters ◽  
Input Unit ◽  
Efficient Operation ◽  
Electric Circuits ◽  
Electronic Neuron

This article studies the implementation of some well-known principles of information work of biological systems in the input unit of the neuroprocessor, including spike coding of information used in models of neural networks of the latest generation.<br> The development of modern neural network IT gives rise to a number of urgent tasks at the junction of several scientific disciplines. One of them is to create a hardware platform&nbsp;— a neuroprocessor for energy-efficient operation of neural networks. Recently, the development of nanotechnology of the main units of the neuroprocessor relies on combined memristor super-large logical and storage matrices. The matrix topology is built on the principle of maximum integration of programmable links between nodes. This article describes a method for implementing biomorphic neural functionality based on programmable links of a highly integrated 3D logic matrix.<br> This paper focuses on the problem of achieving energy efficiency of the hardware used to model neural networks. The main part analyzes the known facts of the principles of information transfer and processing in biological systems from the point of view of their implementation in the input unit of the neuroprocessor. The author deals with the scheme of an electronic neuron implemented based on elements of a 3D logical matrix. A pulsed method of encoding input information is presented, which most realistically reflects the principle of operation of a sensory biological neural system. The model of an electronic neuron for selecting ranges of technological parameters in a real 3D logic matrix scheme is analyzed. The implementation of disjunctively normal forms is shown, using the logic function in the input unit of a neuroprocessor as an example. The results of modeling fragments of electric circuits with memristors of a 3D logical matrix in programming mode are presented.<br> The author concludes that biomorphic pulse coding of standard digital signals allows achieving a high degree of energy efficiency of the logic elements of the neuroprocessor by reducing the number of valve operations. Energy efficiency makes it possible to overcome the thermal limitation of the scalable technology of three-dimensional layout of elements in memristor crossbars.

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